K9F3208W0A- SAMSUNG [Samsung semiconductor], K9F3208W0A- Datasheet - Page 24

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K9F3208W0A-

Manufacturer Part Number
K9F3208W0A-
Description
4M x 8 Bit NAND Flash Memory
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
K9F3208W0A-TCB0, K9F3208W0A-TIB0
Figure 9. Read ID Operation
Table3. Device Status
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (E3h) respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to
"1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is
high. Refer to table 3 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted to by the command register. The R/B pin transitions to low for t
not necessary for normal operation. Refer to Figure 10 below.
Figure 10. RESET Operation
R/B
I/O
CLE
CE
WE
ALE
RE
I/O
0
0
~
~
7
7
Operation Mode
FFh
90h
Address. 1 cycle
00h
After Power-up
t
CLR
t
Read 1
WHR
t
AR1
t
RST
24
t
t
READID
CEA
RST
after the Reset command is written. Reset command is
Maker code
ECh
Waiting for next command
FLASH MEMORY
After Reset
Device code
E3h

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