EP2S15 ALTERA [Altera Corporation], EP2S15 Datasheet - Page 144

• Manufacturer Part Number: EP2S15
• Description: Stratix II Device Family
• Manufacturer: ALTERA [Altera Corporation]

Operating Conditions
5–8
Stratix II Device Handbook, Volume 1
Note to
(1)
V
V
V
V
V
R
V
V
V
V
V
R
Table 5–10. 2.5-V LVDS I/O Specifications
Table 5–11. 3.3-V LVDS I/O Specifications
Symbol
Symbol
CCIO
ID
ICM
OD
OCM
CCIO
ID
ICM
OD
OCM
L
L
The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, VCC_PLL_OUT should be connected to 3.3 V.
(1)
Table
I/O supply voltage for left and
right I/O banks (1, 2, 5, and
6)
Input differential voltage
swing (single-ended)
Input common mode voltage
Output differential voltage
(single-ended)
Output common mode
voltage
Receiver differential input
discrete resistor (external to
Stratix II devices)
I/O supply voltage for top
and bottom PLL banks (9,
10, 11, and 12)
Input differential voltage
swing (single-ended)
Input common mode voltage
Output differential voltage
(single-ended)
Output common mode
voltage
Receiver differential input
discrete resistor (external to
Stratix II devices)
5–11:
Parameter
Parameter
R
R
R
R
L
L
L
L
= 100 Ω
= 100 Ω
= 100 Ω
= 100 Ω
Conditions
Conditions
Minimum
Minimum
2.375
1.125
3.135
100
200
250
100
200
250
840
90
90
Typical
Typical
2.500
1,250
3.300
1,250
350
100
350
100
Altera Corporation
Maximum
Maximum
CCINT
2.625
1,800
1.375
3.465
1,800
1,570
900
450
110
900
710
110
, not V
May 2007
CCIO
Unit
Unit
mV
mV
mV
mV
mV
mV
mV
V
V
V
Ω
Ω
.