IS61LV256-15JL-TR ISSI, IS61LV256-15JL-TR Datasheet - Page 7

• Manufacturer Part Number: IS61LV256-15JL-TR
• Description: Semiconductors and Actives, ic, speed, Memory
• Manufacturer: ISSI

WRITE CYCLE NO. 3
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
06/06/05
WRITE CYCLE NO. 2
IS61LV256
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
ADDRESS
D
D
OUT
OUT
WE
D
WE
OE
D
CE
OE
CE
IN
IN
LOW
LOW
LOW
t
SA
t
DATA UNDEFINED
(WE Controlled, OE is LOW During Write Cycle)
DATA UNDEFINED
(WE Controlled, OE is HIGH During Write Cycle)
SA
V
IH
.
VALID ADDRESS
t
t
t
t
AW
AW
HZWE
HZWE
VALID ADDRESS
t
t
PWE1
WC
t
t
PWE2
WC
HIGH-Z
HIGH-Z
t
t
SD
SD
DATA
DATA
IN
IN
(1)
(1,2)
VALID
VALID
t
t
HD
HD
t
t
LZWE
LZWE
t
t
HA
HA
CE_WR2.eps
CE_WR3.eps
ISSI
®
7