CY7C4292V-15ASCT Cypress Semiconductor, CY7C4292V-15ASCT Datasheet - Page 4

• Manufacturer Part Number: CY7C4292V-15ASCT
• Manufacturer: Cypress Semiconductor

Document #: 38-06014 Rev. *B
and WEN are LOW. The fifth LOW-to-HIGH transition of
WCLK while LD and WEN are LOW writes data to the empty
LSB register again. Figure 1 shows the registers sizes and
default values for the various device types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the LD input HIGH, the FIFO is returned to normal read and
write operation. The next time LD is brought LOW, a write
operation stores data in the next offset register in sequence.
The contents of the offset registers can be read to the data
outputs when LD is LOW and REN is LOW. LOW-to-HIGH
transitions of RCLK read register contents to the data outputs.
Writes and reads should not be performed simultaneously on
the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable Almost Empty flag (PAE) and programmable
Almost Full flag (PAF) states are determined by their corre-
sponding offset registers and the difference between the read
and write pointers.
Table 1. Writing the Offset Registers
Note:
1.
8
8
8
8
LD
Figure 1. Offset Register Location and Default Values
0
0
1
1
The same selection sequence applies to reading from the registers. REN is enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
7
7
7
7
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
WEN
64K × 9
0
1
0
1
Default Value = 000h
Default Value = 000h
(MSB)
(MSB)
WCLK
[1]
0
0
0
0
No Operation
Write Into FIFO
No Operation
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
8
8
8
8
7
7
Selection
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
128K × 9
Default Value = 000h
Default Value = 000h
(MSB)
(MSB)
0
0
0
0
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is
referred to as n and determines the operation of PAE. PAE is
synchronized to the LOW-to-HIGH transition of RCLK by one
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
RCLK when the FIFO contains (n+1) or greater unread words.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAF is synchro-
nized to the LOW-to-HIGH transition of WCLK by one flip-flop
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4282V (64K – m) and
CY7C4292V (128K – m). PAF is set HIGH by the LOW-to-
HIGH transition of WCLK when the number of available
memory locations is greater than m.
Flag Operation
The CY7C4282V/92V devices provide four flag pins to indicate
the condition of the FIFO contents. All flags operate synchro-
nously.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, i.e., it is exclu-
sively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN. EF is synchronized to RCLK,
i.e., it is exclusively updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C4282V/92V features programmable Almost Empty
and Almost Full Flags. Each flag can be programmed
(described in the Programming section) a specific distance
from the corresponding boundary flags (Empty or Full). When
the FIFO contains the number of words or fewer for which the
flags have been programmed, the PAF or PAE will be
asserted, signifying that the FIFO is either Almost Full or
Almost Empty. See Table 2 for a description of programmable
flags.
CY7C4282V
CY7C4292V
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