CY7C4292V-15ASCT Cypress Semiconductor, CY7C4292V-15ASCT Datasheet - Page 9

• Manufacturer Part Number: CY7C4292V-15ASCT
• Manufacturer: Cypress Semiconductor

Document #: 38-06014 Rev. *B
Switching Waveforms
Notes:
14. t
15. t
Read Cycle Timing
Write Cycle Timing
edge of RCLK and the rising edge of WCLK is less than t
rising edge of WCLK and the rising edge of RCLK is less than t
Q
D
SKEW1
SKEW1
0
0
WCLK
WCLK
RCLK
RCLK
WEN
–D
–Q
WEN
REN
REN
OE
FF
EF
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
is also the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
17
17
t
ENS
t
OLZ
t
SKEW1
t
ENH
t
[14]
t
CLKH
CLKH
t
t
t
WFF
A
REF
t
OE
SKEW1
SKEW2
t
t
, then FF may not change state until the next WCLK rising edge.
CLK
CLK
t
SKEW1
NO OPERATION
, then EF may not change state until the next RCLK rising edge.
[15]
t
DS
t
CLKL
t
CLKL
t
ENS
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
t
OHZ
NO OPERATION
CY7C4282V
CY7C4292V
Page 9 of 15
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