LFE2-6E-5TN144CES Lattice Semiconductor, LFE2-6E-5TN144CES Datasheet - Page 19

• Manufacturer Part Number: LFE2-6E-5TN144CES
• Description: Semiconductors and Actives, programmable, Programmable Logic (FPGAs, PALs, CPLDs ...), gate
• Manufacturer: Lattice Semiconductor

Lattice Semiconductor
The secondary clock muxes are located in the center of the device. Figure 2-16 shows the mux structure of the
secondary clock routing.
Figure 2-15. Secondary Clock Regions ECP2-50
Figure 2-16. Per Region Secondary Clock Selection
SC0
24:1
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
I/O Bank 0
I/O Bank 5
Region 1
Region 2
Region 3
Region 4
SC1
24:1
Secondary Clock Feedlines: 8 PIOs + 16 Routing
8 Secondary Clocks (SC0 to SC7) per Region
SC2
24:1
SC3
24:1
Clock/Control
SC4
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
2-16
24:1
I/O Bank 1
I/O Bank 4
Region 5
Region 6
Region 7
Region 8
SC5
24:1
LatticeECP2/M Family Data Sheet
SC6
24:1
SC7
24:1
Vertical Routing
Channel Regional
Boundary
DSP Row
Regional
Boundary
DSP Row
Regional
Boundary
EBR Row
Regional
Boundary
Architecture