LFE2-6E-5TN144CES Lattice Semiconductor, LFE2-6E-5TN144CES Datasheet - Page 40

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LFE2-6E-5TN144CES

Manufacturer Part Number
LFE2-6E-5TN144CES
Description
Semiconductors and Actives, programmable, Programmable Logic (FPGAs, PALs, CPLDs ...), gate
Manufacturer
Lattice Semiconductor
Datasheet
Lattice Semiconductor
Figure 2-35. Edge Clock, DLL Calibration and DQS Local Bus Distribution
Spans 16 PIOs
Spans 18 PIOs
DQS Input
Note: Bank 8 is not shown.
I/O
I/O
B
a
n
7
B
a
n
6
k
k
DDR_DLL
I/O Bank 5
(Left)
I/O Bank 0
2-37
I/O Bank 4
I/O Bank 1
DDR_DLL
(Right)
LatticeECP2/M Family Data Sheet
I/O
I/O
B
B
a
n
k
2
a
n
k
3
ECLK1
ECLK2
Delayed
DQS
Polarity Control
DQSXFER
DQS Delay
Control Bus
Architecture

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