8535AGI-01LFT IDT, 8535AGI-01LFT Datasheet

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8535AGI-01LFT

Manufacturer Part Number
8535AGI-01LFT
Description
Clock Drivers & Distribution 1
Manufacturer
IDT
Datasheet

Specifications of 8535AGI-01LFT

Rohs
yes
Part # Aliases
ICS8535AGI-01LFT
B
G
The ICS8535I-01 is a low skew, high performance 1-to-4
LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The
ICS8535I-01 has two single ended clock inputs. the single
ended clock input accepts LVCMOS or LVTTL input levels
and translate them to 3.3V LVPECL levels. The clock
enable is internally synchronized to eliminate runt clock
pulses on the output during asynchronous assertion/
deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8535I-01 ideal for those applications demand-
ing well defined performance and repeatability.
8535AGI-01
LOCK
ENERAL
CLK_SEL
CLK_EN
CLK0
CLK1
D
IAGRAM
D
ESCRIPTION
0
1
D
LE
Q
LVCMOS/LVTTL-
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
www.idt.com
1
F
P
Four differential 3.3V LVPECL outputs
Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 266MHz
Translates LVCMOS and LVTTL levels to
3.3V LVPECL levels
Output skew: 30ps (maximum)
Part-to-part skew: 250ps (maximum)
Propagation delay: 1.9ns (maximum)
Jitter, RMS: < 0.09ps (typical)
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
EATURES
IN
A
SSIGNMENT
4.4mm x 6.5mm x 0.92mm body package
TO
-3.3V LVPECL F
CLK_SEL
CLK_EN
CLK0
CLK1
V
V
nc
nc
nc
nc
CC
ICS8535I-01
EE
20-Lead TSSOP
G Package
Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ICS8535I-01
L
OW
Q0
nQ0
V
Q1
nQ1
Q2
nQ2
V
Q3
nQ3
CC
CC
ANOUT
S
KEW
REV. F OCTOBER 4, 2010
, 1-
B
UFFER
TO
-4

Related parts for 8535AGI-01LFT

8535AGI-01LFT Summary of contents

Page 1

... LOCK IAGRAM D CLK_EN Q LE CLK0 0 CLK1 1 CLK_SEL 8535AGI-01 LVCMOS/LVTTL- -3.3V LVPECL EATURES Four differential 3.3V LVPECL outputs Selectable CLK0 or CLK1 inputs for redundant and multiple frequency fanout applications CLK0 or CLK1 can accept the following input levels: LVCMOS or LVTTL Maximum output frequency: 266MHz Translates LVCMOS and LVTTL levels to 3 ...

Page 2

... 8535AGI-01 LVCMOS/LVTTL ...

Page 3

... ABLE LOCK NPUT UNCTION ABLE 8535AGI-01 LVCMOS/LVTTL- TO ABLE ...

Page 4

... LVCMOS/LVTTL- 4.6V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the -0. 0.5V CC device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions 50mA beyond those listed in the DC Characteristics or AC Charac- 100mA teristics is not implied ...

Page 5

... 8535AGI-01 LVCMOS/LVTTL -40°C 85° ƒ ...

Page 6

... As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The 8535AGI-01 LVCMOS/LVTTL- -3.3V LVPECL ...

Page 7

... UTPUT OAD EST IRCUIT nQx Qx nQy Qy tsk( UTPUT KEW CLK0, CLK1 nQ0:nQ3 Q0: ROPAGATION ELAY 8535AGI-01 LVCMOS/LVTTL- -3.3V LVPECL EASUREMENT NFORMATION SCOPE PART 1 nQx Qx Qx PART 2 nQy nQx ART TO ART Clock 20% Outputs ...

Page 8

... RTT = – 2)) – 2A. LVPECL O IGURE UTPUT 8535AGI-01 LVCMOS/LVTTL PPLICATION NFORMATION NPUT AND UTPUT INS O : UTPUTS LVPECL O UTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated ...

Page 9

... CLK0 input is selected. The decoupling ca- 3. Ohm Ohm R13 43 R11 LVCMOS 1K F IGURE 8535AGI-01 LVCMOS/LVTTL- TO pacitors should be physically located near the power pin. For ICS8535I-01, the unused clock outputs can be left floating. 3.3V R12 VEE ...

Page 10

... HERMAL ESISTANCE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8535AGI-01 LVCMOS/LVTTL OWER ONSIDERATIONS = 3. 3.465V, which gives worst case results. ...

Page 11

... Pd_L is the power dissipation when the output drives low. Pd_H = [(V – 2V))/ OH_MAX CC_MAX L [(2V - 0.9V)/ 0.9V = 19.8mW Pd_L = [(V – 2V))/ OL_MAX CC_MAX L [(2V - 1.7V)/ 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8535AGI-01 LVCMOS/LVTTL LVPECL RIVER IRCUIT AND – 0.9V CC_MAX – 1.7V CC_MAX - [( ...

Page 12

... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS8535I-01 is: 412 8535AGI-01 LVCMOS/LVTTL ELIABILITY NFORMATION 20 L ...

Page 13

... ACKAGE UTLINE UFFIX FOR T ABLE R EFERENCE 8535AGI-01 LVCMOS/LVTTL- -3.3V LVPECL F TO TSSOP EAD ACKAGE IMENSIONS ...

Page 14

... Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 8535AGI-01 LVCMOS/LVTTL- ...

Page 15

... 8535AGI-01 LVCMOS/LVTTL ...

Page 16

... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 8535AGI-01 LVCMOS/LVTTL- -3.3V LVPECL F TO ...

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