AS4C8M16S-6TAN Alliance Memory, AS4C8M16S-6TAN Datasheet
AS4C8M16S-6TAN
Specifications of AS4C8M16S-6TAN
Related parts for AS4C8M16S-6TAN
AS4C8M16S-6TAN Summary of contents
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... FBGA package -Pb free and Halogen free Overview The AS4C8M16S SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented ...
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... Figure 2. Block Diagram BUFFER CKE CS# RAS# COMMAND DECODER CAS# WE# COLUMN A10/AP COUNTER A0 ADDRESS A9 BUFFER A11 BA0 BA1 REFRESH COUNTER CONTROL SIGNAL GENERATOR LDQM, UDQM MODE REGISTER 2 AS4C8M16S CELL ARRAY (BANK #A) Column Decoder DQ0 DQ Buffer DQ15 CELL ARRAY (BANK #B) Column Decoder ...
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... FEBRUARY 2011 Pin Descriptions Table 3. Pin Details of AS4C8M16S Symbol Type CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal ...
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... CLK. The I/Os are maskable during Reads and Writes. NC/RFU - No Connect: These pins should be left unconnected. V Supply DQ Power: Provide isolated power to DQs for improved noise immunity. DDQ ( 3.3V± 0. Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. SSQ ( Supply Power Supply: +3.3V ± 0. Supply Ground SS 4 AS4C8M16S ...
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... ( AS4C8M16S CS# RAS# CAS# WE 0-9, Column address (A0 ~ A8) Column ...
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... NOP AutoPrecharge Activate RAS# - Cycle time AutoPrecharge Begin (Burst Length = n, CAS# Latency = 3) (max.). Therefore, the precharge function must be performed RAS (max.). At the end of precharge, the precharged bank is still in the idle RCD 6 AS4C8M16S By (min.) RCD Tn+4 Tn+5 Tn+6 Bank A Row Addr. ) RRD Bank A NOP NOP Activate Don’ ...
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... Length = 4, CAS# Latency = NOP NOP NOP NOP DOUT A DOUT B DOUT B DOUT DOUT B 3 DOUT A DOUT B DOUT (Burst Length = 4, CAS# Latency = AS4C8M16S T7 T8 NOP NOP 3 DOUT NOP NOP NOP 2 DOUT B DOUT ...
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... Length ≧ 4, CAS# Latency = READ A NOP NOP WRITE B NOP DIN B DIN B 0 Must be Hi-Z before the Write Command (Burst Length ≥ 4, CAS# Latency = 2) 8 AS4C8M16S NOP NOP NOP DIN A DIN A DIN A DIN NOP NOP ...
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... Latency = 2, 3) (min.) before the Write command is RCD NOP NOP NOP NOP DIN A DIN A DIN A don’t care (Burst Length = 4) 9 AS4C8M16S Bank Row NOP Activate NOP DOUT A 3 Don’t Care NOP NOP NOP ...
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... Input data must be removed from the DQ at least one clock cycle before the Read data appears on the outputs to avoid data contention (Burst Length = 4, CAS# Latency = 2, 3) rounded up to the next whole number. In addition, the DQM signals 10 AS4C8M16S T7 T8 NOP NOP NOP T7 ...
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... Don’t Care + t (min.)}. At full-page burst, only the write operation Write A NOP NOP NOP NOP Auto Precharge t DAL DIN A DIN Begin AutoPrecharge Bank can be reactivated at completion AS4C8M16S T7 NOP Bank A NOP NOP Activate DAL (Burst Length = 2) ...
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... All other Reserved MRD Address Key t RP Mode Register Set Command 12 AS4C8M16S Burst Length A3 Burst Type 0 Sequential 1 Interleave Burst Length Full Page (Sequential T10 Any Don’t Care Command ...
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... AS4C8M16S Interleave Not Support ...
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... CAS# latency (refer to the following figure). The termination of a write burst is shown in the following figure. A4 CAS# Latency 0 Reserved 1 Reserved 0 2 clocks 1 3 clocks X Reserved Test Mode normal mode Vendor Use Only Vendor Use Only 14 AS4C8M16S ...
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... NOP NOP Burst Stop don’t care DIN A DIN (min.). To provide the AutoRefresh command, all banks need to RC (min), must be met before successive auto refresh operations are RP 15 AS4C8M16S NOP NOP NOP DOUT NOP NOP NOP ...
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... During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device selection, byte selection and bus control in a memory system. (min.) because time is required for the XSR (min.) is required when the device exits from PDE 16 AS4C8M16S ...
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... Input/Output Capacitance I/O Note: These parameters are periodically sampled and are not 100% tested 0~70°C) A Min. 3.0 3.0 2 ≤ OUT DDQ 2.4 = -2mA ) － = 2mA ) = 25°C) A Min. 17 AS4C8M16S Rating Unit Note -6/7 - 1 -1 ° 125 °C 1 260 ° Typ. ...
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... T Symbol I DD1 I DD2N IH I DD2NS IH I DD2P I DD2PS (min DD3N I = ∞ DD3NS CK I DD4 I DD5 I ≤ 0.2V DD6 - 0. AS4C8M16S = 0~70° Unit Note Max. 3 120 110 140 130 3 200 200 ...
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... CL CL 2.5 - 2 VIH (Max) = 4.6V for pulse width ≤ 3ns. VIL (Min) = -1.5V for pulse SS 19 AS4C8M16S -7 Unit Note Min Max 100k - 5.4 ...
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... Transition (rise and fall) of input signals are -0.5) ns should be added to the parameter & (simultaneously) when CKE= “L”, DQM= “H” and all input and V DD DDQ levels) to ensure DQ output is in high impedance AS4C8M16S 1ns 1.4V 1. Ω 30pF ...
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... RAy RBx CBx RAy t t DAL Ax2 Bx0 Bx1 Bx2 Bx3 Activate Write with Activate Auto Precharge Command Bank B Command Bank A Bank B 21 AS4C8M16S CAy Ay1 Ay2 Ay0 Ay3 Write Precharge Command Command Bank A Bank A Don’t Care ...
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... Ax0 Ax1 t OH Activate Read Read with Command Command Auto Precharge Command Bank B Bank A Command Bank B 22 AS4C8M16S T11 T12 T13 T14 T15 T16 Begin Auto t IH Precharge Bank B RAy RAy t RP Bx0 Bx1 t HZ Activate Precharge Command ...
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... Precharge All Auto Refresh Command Command T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Auto Refresh Command 23 AS4C8M16S RAx RAx CAx t RCD Ax0 Ax1 Activate Read Command Command Bank A Bank A Don’t Care ...
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... Mode Register Stable for 200 µs Set Command Note(*):The Auto Refresh command can be issue before or after Mode Register Set command Minimum for 2 Refresh Cycles are required (*) 2nd Auto Refresh 1st Auto Refresh Command Command 24 AS4C8M16S (*) Any Command Don’t Care ...
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... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 t XSR *Note 5 *Note *Note 6 *Note 7 Hi-Z Self Refresh Exit is required before exit from SelfRefresh. RAS 25 AS4C8M16S *Note 8 t PDE *Note 9 Auto Refresh Don’t Care ...
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... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, RAx CAx A11 DQM Hi-Z DQ Ax0 Activate Read Clock Suspend Cammand Command 1 Cycle Bank A Bank Ax1 Ax2 Ax3 Clock Suspend Clock Suspend 3 Cycles 2 Cycles 26 AS4C8M16S Don’t Care ...
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... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, RAx CAx A11 DQM Hi-Z DQ Activate Read Cammand Command Bank A Bank Ax1 Ax0 Ax2 Ax3 Clock Suspend Clock Suspend Clock Suspend 2 Cycles 3 Cycles 1 Cycle 27 AS4C8M16S Don’t Care ...
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... CAx A11 DQM Hi-Z DQ DAx0 DAx1 Activate Clock Suspend Cammand 1 Cycle Bank A Write Command Bank T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 DAx2 DAx3 Clock Suspend Clock Suspend 2 Cycles 3 Cycles 28 AS4C8M16S Don’t Care ...
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... T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Valid t HZ Ax0 Ax1 Ax2 Ax3 Clock Suspension Clock Suspension Precharge Command End Start Bank A Power Down Mode Entry 29 AS4C8M16S t PDE PRECHARGE STANDBY Power Down Mode Exit Any Commad Don’t Care ...
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... Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Activate Read Cammand Command Bank A Bank A CAx CAy Ay0 Ay1 Ay2 Ay3 Read Read Precharge Command Command Command Bank A Bank A Bank A 30 AS4C8M16S RAz RAz CAz Az0 Activate Read Command Command Bank A Bank A Don’t Care ...
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... Activate Read Cammand Command Bank A Bank A CAx CAy Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Read Read Precharge Command Command Command Bank A Bank A Bank A 31 AS4C8M16S RAz RAz CAz Activate Read Command Command Bank A Bank A Don’t Care ...
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... DBw0 DBw1 DBw2 DBw3 DBy3 Activate Write Cammand Command Bank B Bank B CBx CBy DBx0 DBx1 DBy0 DBy1 DBy2 Write Write Precharge Command Command Command Bank B Bank B Bank B 32 AS4C8M16S RBz RBz CBz DBz0 DBz1 Activate Write Command Command Bank B Bank B Don’t Care ...
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... Bank B RAx RBy RAx RBy CAx t RP Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Read Activate Activate Command Command Command Bank A Bank A Bank B Precharge Command Bank B 33 AS4C8M16S CBy Ax3 Ax4 Ax5 Ax6 Ax7 Read Command Bank B Don’t Care ...
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... RAx CAx t RP Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Activate Read Precharge Command Command Command Bank A Bank A Bank B 34 AS4C8M16S RBy RBy CBy Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 Activate Read Precharge Command Command Command Bank B Bank B Bank A ...
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... RBx RBx CBx WR* DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Activate Precharge Write Command Command Command Bank B Bank B Bank A 35 AS4C8M16S RAy RAy CAy t WR* Activate Write Precharge Command Command Command Bank A Bank A Bank B Don’t Care ...
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... T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy Ax2 Ax3 DAy0 DAy1 DAy3 Write The Write Data Command is Masked with a Bank A Zero Clock Latency 36 AS4C8M16S CAz Az0 Az1 Az3 The Read Data Read is Masked w ith a Command Two Clock Bank A Latency ...
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... T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy Ax1 Ax2 Ax3 Ax0 DAy0 DAy1 DAy3 Write The Write Data Command is Masked with a Bank A Zero Clock Latency 37 AS4C8M16S CAz Az1 Az3 Az0 The Read Data is Masked with a Two Clock Latency Read Command Bank A Don’t Care ...
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... Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3 Read Read Read Read Command Command Command Command Command Bank A Bank B Bank B Bank B 38 AS4C8M16S CBz Read Precharge Command Bank B Bank B Precharge Command Bank A Don’t Care ...
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... CBy CBz CAy t AC Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 By0 By1 Bz0 Read Read Read Read Command Command Command Command Command Bank B Bank B Bank A Bank B 39 AS4C8M16S Bz1 Ay0 Ay1 Ay2 Ay3 Precharge Precharge Command Bank A Bank B Don’t Care ...
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... Bank A Activate Command Bank B (Burst Length=4) CBw CBx CBy CAy CBz t WR Write Write Write Write Write Command CommandCommand CommandCommand Bank B Bank B Bank B Bank A Bank B 40 AS4C8M16S AS4C8M16S t WR DBz1 DBz2 DBz3 Precharge Command Bank B Precharge Command Bank A Don’t Care ...
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... Bx0 Bx1 Bx2 Bx3 Ay0 Read with Activate Command Auto Precharge Bank B Command Read with Bank B Auto Precharge Command Bank A 41 AS4C8M16S Begin Auto Precharge Bank A RAz CBy RAz Ay1 Ay2 Ay3 By0 By1 By2 Activate Command Bank A Read with Auto Precharge ...
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... Begin Auto Precharge Precharge Bank A Bank B RBy CBx CAy RBy t RP Read with Read with Activate Auto Precharge Auto Precharge Command Command Command Bank B Bank A Bank B 42 AS4C8M16S CBy By0 By1 By2 Read with Auto Precharge Command Bank B Don’t Care ...
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... DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 Activate Write with Write with Command Auto Precharge Auto Precharge Command Bank B Command Bank B Bank A 43 AS4C8M16S Begin Auto Precharge Bank A RBy RBy CBy DBy0 DBy1 DBy2 DBy3 Write with Auto Precharge Command Bank B Don’ ...
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... Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Read Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address 44 AS4C8M16S RBy RBy t RP Precharge Activate Command Command Bank B Bank B Burst Stop Command ...
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... Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Read Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address 45 AS4C8M16S RBy RBy t RP Precharge Activate Command Command Bank B Bank B Burst Stop Command ...
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... Command Bank B Burst Stop Command Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address 46 AS4C8M16S RBy RBy Data is ignored Precharge Activate Command Command Bank B Bank B Don’t Care ...
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... T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy CAz DAy1 DAy2 Ax1 Ax2 Ax3 DAy3 DAy0 DAy1 Lower Byte Write Read Upper Byte Command is masked Command is masked Bank A Bank A 47 AS4C8M16S Az1 Az2 Az0 Az1 Az2 Az3 Lower Byte Lower Byte is masked is masked Don’t Care ...
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... Bu3 Au2 Au3 Au1 Activate Activate Command Command Bank B Bank A Read Read Bank A Bank B with Auto with Auto Precharge Precharge 48 AS4C8M16S Begin Auto Begin Auto Precharge Precharge Bank B Bank A RBw CAv RBw t RP Bv3 Av0 Av2 Av3 Bv0 Bv1 Bv2 Av1 ...
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... Bank B Bank B Read Command Bank A (Burst Length=Full Page, CAS# Latency=2) CBy CAz CBz Read Read Read Command Command Command Bank B Bank A Bank B Read Command Bank A 49 AS4C8M16S RBw RBw t RP Precharge Command Bank B (Precharge Temination) Activate Command Bank B Don’t Care ...
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... Bank B Write Command Bank A RAy RAy CAy t RP Ay0 Ay1 Activate Read Precharge Command Command Command Bank A Bank A Bank A 50 AS4C8M16S RBw RBw Precharge Command Bank B (Precharge Temination) Activate Write Data Command are masked Bank B RAz RAz t RP Ay2 ...
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... Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash. 4. Controlling dimension Dimension in mm Nom Max Min --- 0.047 --- --- 0.008 0.05 0.043 0.9 0.018 0.25 0.008 0.12 0.88 22.09 0.405 10.03 --- --- 0.471 11.56 --- 0.024 0.4 --- --- --- --- --- 0.004 --- 8 ° 0 ° --- 51 AS4C8M16S θ° Nom Max --- 1.2 --- 0.2 1.0 1.1 0.35 0.45 0.165 0.21 22.22 22.35 10.16 10.29 0.8 --- 11.76 11.96 0.5 0.6 0.84 --- 0.71 --- --- 0.1 8 ° --- ...
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... Dimension in inch Symbol Min -- A A1 0.012 0.014 0.016 A2 0.024 0.026 0.028 c 0.007 0.008 0.010 D 0.311 0.315 0.319 E 0.311 0.315 0.319 0.016 0.018 0.020 F -- Bottom View Dimension in mm Nom Max Min Nom -- 0.047 -- 0.30 0.35 0.61 0.66 0.17 0.21 7.90 8.00 7.90 8.00 0.252 -- -- 6.40 0.252 -- -- 6.40 0.031 -- -- 0.80 0.40 0.45 0.126 -- -- 3.20 52 AS4C8M16S Max -- 1.20 0.40 0.71 0.25 8.10 8. 0.50 -- ...
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... VCC Package Range 3.3V+/-0.3V 54 TSOP II 3.3V+/-0.3V 54 TSOP II 3.3V+/-0.3V 54 TSOP II 3.3V+/-0.3V 54 TFBGA -7 Package 54 pin TSOP II Temperature Range Speed C = Commercial 54pin TFBGA 53 AS4C8M16S Speed Operating Temp MHz Commercial 166 Industrial 166 Commercial 143 Commercial 143 Lead Free RoHS compliant part (0 - 70° Industrial ...