AS4C8M16S-7TCN ALLIANCE MEMORY, AS4C8M16S-7TCN Datasheet

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... Interface: LVTTL • 54-pin 400 mil plastic TSOP II package - Pb free and Halogen free Overview The AS4C8M16S SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented ...

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... COLUMN A10/AP COUNTER A0 ADDRESS A9 BUFFER A11 BA0 BA1 REFRESH COUNTER CONTROL SIGNAL GENERATOR LDQM, UDQM MODE REGISTER 2 AS4C8M16S CELL ARRAY (BANK #A) Column Decoder DQ0 DQ Buffer DQ15 CELL ARRAY (BANK #B) Column Decoder CELL ARRAY (BANK #C) Column Decoder CELL ARRAY (BANK #D) Column Decoder ...

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... FEBRUARY 2011 Pin Descriptions Table 3. Pin Details of AS4C8M16S Symbol Type Clock: CLK is driven by the system clock. All SDRAM input signals are sampled CLK Input on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If ...

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... No Connect: These pins should be left unconnected. NC/RFU - DQ Power: Provide isolated power to DQs for improved noise immunity. V Supply DDQ ( 3.3V± 0. Ground: Provide isolated ground to DQs for improved noise immunity. V Supply SSQ ( Power Supply: +3.3V ± 0.3V V Supply DD Ground V Supply SS 4 AS4C8M16S ...

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... Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode. Table 4. Truth Table (Note (1), (2)) CKE CKE DQM BA A 0,1 n Row address ( ( ( ( code ( ( AS4C8M16S A CS# RAS# CAS# WE# 10 0-9, Column address (A0 ~ A8) Column address ( ...

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... RC AutoPrecharge Begin (Burst Length = n, CAS# Latency = 3) (max.). Therefore, the precharge function must be performed RAS (max.). At the end of precharge, the precharged bank is still in the idle (min.) before the Read command is RCD 6 AS4C8M16S (min.) RCD Tn+4 Tn+5 Tn+6 Bank A Row Addr. ) RRD Bank A ...

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... NOP NOP NOP NOP DOUT A DOUT A DOUT A DOUT DOUT A DOUT A DOUT A DOUT (Burst Length = 4, CAS# Latency = NOP NOP NOP NOP DOUT A DOUT B DOUT B DOUT B DOUT DOUT A DOUT B DOUT B DOUT (Burst Length = 4, CAS# Latency = AS4C8M16S T7 T8 NOP NOP NOP NOP NOP 3 DOUT ...

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... Must be Hi-Z before the Write Command (Burst Length ≧ 4, CAS# Latency = READ A NOP NOP NOP WRITE B DIN B DIN B 0 Must be Hi-Z before the Write Command (Burst Length ≥ 4, CAS# Latency = 2) 8 AS4C8M16S NOP NOP NOP NOP DIN A DIN A DIN A DIN NOP NOP ...

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... DOUT A DOUT DOUT A DOUT A DOUT (CAS# Latency = 2, 3) (min.) before the Write command is RCD NOP NOP NOP NOP DIN A DIN A DIN A don’t care (Burst Length = 4) 9 AS4C8M16S Bank Row NOP Activate NOP DOUT A 3 Don’t Care NOP NOP NOP ...

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... Input data must be removed from the DQ at least one clock cycle before the Read data appears on the outputs to avoid data contention (Burst Length = 4, CAS# Latency = 2, 3) rounded up to the next whole number. In addition, the DQM signals 10 AS4C8M16S T7 T8 NOP NOP NOP T7 ...

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... NOP NOP Precharge BANK(S) ROW tWR Don’t Care + t (min.)}. At full-page burst, only the write operation Write A NOP NOP NOP NOP Auto Precharge t DAL DIN A DIN Begin AutoPrecharge Bank can be reactivated at completion AS4C8M16S T7 NOP Bank A NOP NOP Activate DAL (Burst Length = 2) ...

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... CAS# Latency BT A7 Test Mode 0 Normal 0 Vendor Use Only 1 Vendor Use Only All other Reserved MRD Address Key t RP Mode Register Any Set Command Command 12 AS4C8M16S Burst Length A3 Burst Type 0 Sequential 1 Interleave Burst Length Full Page (Sequential T10 Don’t Care ...

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... Sequential 1 Interleave • Burst Definition, Addressing Sequence of Sequential and Interleave Mode Table 8. Burst Definition Start Address Burst Length Full page location = 0-511 A0 Burst Length Reserved 1 Reserved 0 Reserved 1 Full Page Sequential n+1, n+2, n+3, …511 … n-1, n, … 13 AS4C8M16S Interleave Not Support ...

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... CAS# latency (refer to the following figure). The termination of a write burst is shown in the following figure. A4 CAS# Latency 0 Reserved 1 Reserved 0 2 clocks 1 3 clocks X Reserved Test Mode normal mode Vendor Use Only Vendor Use Only 14 AS4C8M16S ...

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... Length ＞ 4, CAS# Latency = NOP NOP NOP Burst Stop DIN A DIN A don’t care (min.). To provide the AutoRefresh command, all banks need to RC (min), must be met before successive auto refresh operations are RP 15 AS4C8M16S NOP NOP NOP DOUT NOP NOP NOP (Burst Length = X) ...

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... During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device selection, byte selection and bus control in a memory system. (min.) because time is required for the XSR (min.) is required when the device exits from PDE 16 AS4C8M16S ...

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... Input/Output Capacitance I/O Note: These parameters are periodically sampled and are not 100% tested 0~70°C) A Min. 3.0 3.0 2 ≤ OUT DDQ 2.4 = -2mA ) － = 2mA ) = 25°C) A Min. 17 AS4C8M16S Rating Unit Note -6/7 - 1 -1 ° 125 °C 1 260 ° Typ ...

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... CKE ≤ 0.2V ; for other inputs V ≥ (VDD = 3.3V ± 0.3V, T Symbol I DD1 I DD2N IH I DD2NS IH I DD2P I DD2PS (min DD3N = ∞ I DD3NS CK I DD4 I DD5 I ≤ 0.2V DD6 - 0. AS4C8M16S = 0~70° Unit Note Max. 3 120 110 140 130 3 200 200 ...

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... Power-up sequence is described in Note 11. 6. A.C. Test Conditions -6 Min Max 100k CL CL 2.5 - 2 VIH (Max) = 4.6V for pulse width ≤ 3ns. VIL (Min) = -1.5V for pulse SS 19 AS4C8M16S -7 Unit Note Min Max 100k - IS+ CK µ ...

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... Figure 18.2 LVTTL A.C. Test Load (B) and V . Transition (rise and fall) of input signals are -0.5) ns should be added to the parameter & and V (simultaneously) when CKE= “L”, DQM= “H” and all input DD DDQ levels) to ensure DQ output is in high impedance AS4C8M16S 1ns 1.4V 1.4V 50 Ω 30pF ...

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... RBx CBx RAy t t DAL Ax3 Bx0 Bx1 Bx2 Bx3 Activate Write with Activate Command Auto Precharge Command Bank B Command Bank A Bank B 21 AS4C8M16S T20 T21 T22 CAy Ay0 Ay1 Ay2 Ay3 Write Precharge Command Command Bank A Bank A Don’t Care ...

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... RAS Ax0 Ax1 t OH Activate Read Read with Command Auto Precharge Command Bank B Bank A Command Bank B 22 AS4C8M16S T11 T12 T13 T14 T15 T16 Begin Auto t IH Precharge Bank B RAy RAy t RP Bx0 Bx1 t HZ Precharge Activate Command Command Bank A Bank A ...

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... A0-A9, A11 t RP DQM DQ Precharge All Auto Refresh Command Command T11 T12 T13 T14 T15 T16 T17 T18 T19 Auto Refresh Command 23 AS4C8M16S T20 T21 T22 RAx RAx CAx t RCD Ax0 Ax1 Activate Read Command Command Bank A Bank A Don’t Care ...

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... Note(*):The Auto Refresh command can be issue before or after Mode Register Set command T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Minimum for 2 Refresh Cycles are required (*) 2nd Auto Refresh 1st Auto Refresh Command Command 24 AS4C8M16S (*) Any Command Don’t Care ...

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... AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 t XSR *Note 5 *Note *Note 6 *Note 7 Hi-Z Self Refresh Exit is required before exit from SelfRefresh. RAS 25 AS4C8M16S *Note 8 t PDE *Note 9 Auto Refresh Don’t Care ...

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... RAx CAx A11 DQM Hi-Z DQ Ax0 Activate Read Clock Suspend Cammand Command 1 Cycle Bank A Bank A T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 t HZ Ax1 Ax2 Ax3 Clock Suspend Clock Suspend 3 Cycles 2 Cycles 26 AS4C8M16S T22 Don’t Care ...

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... RAx CAx A11 DQM Hi-Z DQ Activate Read Cammand Command Bank A Bank A T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t HZ Ax1 Ax2 Ax3 Ax0 Clock Suspend Clock Suspend Clock Suspend 3 Cycles 1 Cycle 2 Cycles 27 AS4C8M16S Don’t Care ...

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... A0-A9, RAx CAx A11 DQM Hi-Z DQ DAx0 DAx1 Activate Clock Suspend Cammand 1 Cycle Bank A Write Command Bank A T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 DAx2 DAx3 Clock Suspend Clock Suspend 2 Cycles 3 Cycles 28 AS4C8M16S Don’t Care ...

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... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Valid t HZ Ax0 Ax1 Ax2 Ax3 Precharge Clock Suspension Clock Suspension Command End Start Bank A Power Down Mode Entry 29 AS4C8M16S t PDE PRECHARGE STANDBY Power Down Mode Exit Any Commad Don’t Care ...

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... Command Bank A Bank A T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAx CAy Read Read Precharge Command Command Command Bank A Bank A Bank A 30 AS4C8M16S RAz RAz CAz Az0 Activate Read Command Command Bank A Bank A Don’t Care ...

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... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAx CAy Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Read Read Precharge Command Command Command Bank A Bank A Bank A 31 AS4C8M16S RAz RAz CAz Activate Read Command Command Bank A Bank A Don’t Care ...

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... Bank B Bank B T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CBx CBy Write Write Precharge Command Command Command Bank B Bank B Bank B 32 AS4C8M16S RBz RBz CBz DBz0 DBz1 Activate Write Command Command Bank B Bank B Don’t Care ...

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... RAx RBy RAx RBy CAx t RP Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Activate Read Activate Command Command Command Bank A Bank A Bank B Precharge Command Bank B 33 AS4C8M16S T20 T21 T22 CBy Ax4 Ax5 Ax6 Ax7 Read Command Bank B Don’t Care ...

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... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAx RBy RAx CAx RBy t RP Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 Activate Read Precharge Activate Command Command Command Command Bank A Bank A Bank B Bank B 34 AS4C8M16S CBy By0 Read Precharge Command Command Bank B Bank A Don’t Care ...

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... T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RBx RAy RBx CBx RAy WR* Activate Precharge Write Activate Command Command Command Command Bank B Bank B Bank A Bank A 35 AS4C8M16S CAy t WR* Write Precharge Command Command Bank A Bank B Don’t Care ...

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... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Write The Write Data Command is Masked with a Bank A Zero Clock Latency 36 AS4C8M16S CAz Az1 Az3 Az0 The Read Data Read is Masked with a Command Two Clock Bank A Latency Don’t Care ...

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... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy Ax1 Ax2 Ax3 Ax0 DAy0 DAy1 DAy3 Write The Write Data Command is Masked with a Bank A Zero Clock Latency 37 AS4C8M16S CAz Az1 Az3 Az0 The Read Data is Masked with a Two Clock Latency Read Command Bank A Don’t Care ...

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... CBy CAy CBz Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3 Read Read Read Read Read Command Command Command Command Command Bank B Bank A Bank B Bank B Bank B 38 AS4C8M16S Precharge Command Bank B Precharge Command Bank A Don’t Care ...

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... CBy CBz CAy t AC Ax0 Ax1 Ax2 Ax3 By0 By1 Bz0 Bx0 Bx1 Read Read Read Read Command Command Command Command Bank B Bank B Bank B Bank A 39 AS4C8M16S Ay1 Ay2 Bz1 Ay0 Ay3 Precharge Precharge Command Command Bank A Bank B Don’t Care ...

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... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CBw CBx CBy CAy CBz t WR Write Write Write Write Write Command Command Command Command Command Bank B Bank B Bank B Bank A Bank B 40 AS4C8M16S AS4C8M16S t WR DBz2 DBz3 Precharge Command Bank B Precharge Command Bank A Don’t Care ...

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... Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 Read with Activate Auto Precharge Command Bank B Command Read with Bank B Auto Precharge Command Bank A 41 AS4C8M16S T21 T22 RAz CBy RAz By0 By1 By2 Activate Command Bank A Read with Auto Precharge Command Bank B Don’t Care ...

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... Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 Read with Read with Activate Auto Precharge Auto Precharge Command Command Command Bank B Bank A Bank B 42 AS4C8M16S CBy By0 By1 By2 Read with Auto Precharge Command Bank B Don’t Care ...

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... CAy t DAL Activate Write with Write with Command Auto Precharge Auto Precharge Bank B Command Command Bank B Bank A 43 AS4C8M16S Begin Auto Precharge Bank A RBy RBy CBy DBy0 DBy1 DBy2 DBy3 Write with Auto Precharge Command Bank B Don’t Care Rev 1.0 ...

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... Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Read Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address 44 AS4C8M16S RBy RBy t RP Bx+6 Bx+3 Bx+4 Bx+5 Precharge Activate ...

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... Bx Bx+1 Bx+2 Read Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address 45 AS4C8M16S RBy RBy t RP Bx+3 Bx+4 Bx+5 Precharge Activate Command Command Bank B ...

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... Command Bank B Burst Stop Command Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address 46 AS4C8M16S RBy RBy Data is ignored Precharge Activate Command Command Bank B Bank B Don’t Care ...

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... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy CAz DAy2 DAy1 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Lower Byte Write Upper Byte Read Command Command is masked is masked Bank A Bank A 47 AS4C8M16S Az1 Az2 Az1 Az3 Az0 Az2 Lower Byte Lower Byte is masked is masked Don’t Care ...

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... Au2 Au3 Bu2 Au1 Activate Activate Command Command Bank B Bank A Read Read Bank A Bank B with Auto with Auto Precharge Precharge 48 AS4C8M16S Begin Auto Begin Auto Precharge Precharge Bank B Bank A RBw CAv RBw t RP Bv3 Av0 Av1 Av2 Av3 Bv0 Bv1 Bv2 ...

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... Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2 Read Read Read Command Command Command Bank B Bank A Bank B Read Command Bank A 49 AS4C8M16S T18 T19 T20 T21 T22 RBw RBw t RP Precharge Command Bank B (Precharge Temination) Activate Command Bank B Don’t Care ...

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... Bank A Bank B Write Command Bank A RAy RAy CAy t RP Ay0 Activate Precharge Read Command Command Command Bank A Bank A Bank A 50 AS4C8M16S RBw RBw Precharge Command Bank B (Precharge Temination) Activate Write Data Command are masked Bank B RAz RAz t RP Ay1 Ay2 Activate ...

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... AS4C8M16S θ° Nom Max --- 1.2 --- 0.2 1.0 1.1 0.35 0.45 0.165 0.21 22.22 22.35 10.16 10.29 0.8 --- 11.76 11.96 0.5 0.6 ...

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... FEBRUARY 2011 ORDERING INFORMATION Alliance Organization AS4C8M16S-6TCN AS4C8M16S-7TCN PART NUMBERING SYSTEM 4M4 8M16S AS4C S= SDRAM SDRAM prefix 128Mb (8Mx16) VCC Package Range 3.3V+/-0.3V 54 TSOP II 3.3V+/-0.3V 54 TSOP II -7 T=TSOP Package 54 pin TSOP II Temperature Range Speed C = Commercial 52 AS4C8M16S Speed Operating Temp ...