IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 62

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
9.2.1 Timing Parameter by Speed Bin (DDR3-1333, DDR3-1600)
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
Cumulative error across n = 13, 14 . . . 49, 50
Data setup time to DQS, DQS# referenced to
Data setup time to DQS, DQS# referenced to
Clock Period Jitter during DLL locking period
Data hold time from DQS, DQS# referenced
DQ and DM Input pulse width for each input
DQS, DQS# rising edge output access time
Minimum Clock Cycle Time (DLL off mode)
DQS, DQS# differential WRITE Postamble
DQS, DQS# differential READ Postamble
DQS, DQS# differential WRITE Preamble
DQS, DQS# to DQ skew, per group, per
DQS,DQS# differential READ Preamble
DQS, DQS# differential output high time
DQ high impedance time from CK, CK#
DQS, DQS# differential output low time
Cycle to Cycle Period Jitter during DLL
DQ low-impedance time from CK, CK#
DQ output hold time from DQS, DQS#
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Absolute clock HIGH pulse width
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Absolute clock LOW pulse width
Cycle to Cycle Period Jitter
Average high pulse width
Average low pulse width
to Vih(dc) / Vil(dc) levels
Absolute Clock Period
Average Clock Period
Vih(ac) / Vil(ac) levels
Vih(ac) / Vil(ac) levels
from rising CK, CK#
Data Strobe Timing
Clock Period Jitter
Duty Cycle Jitter
locking period
Clock Timing
Data Timing
Parameter
access
cycles
tCK(DLL_OFF)
tERR(10per)
tERR(11per)
tERR(12per)
JIT(per, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(nper)
JIT(cc, lck)
tDH(base)
tDS(base)
tDS(base)
tJIT(duty)
tCH(avg)
tCH(abs)
tCK(avg)
tCL(avg)
tCK(abs)
tCL(abs)
tDQSCK
tHZ(DQ)
tLZ(DQ)
JIT(per)
Symbol
tJIT(cc)
tWPRE
tDQSQ
tWPST
AC175
AC150
DC100
tRPRE
tDIPW
tRPST
tQSH
tQSL
tQH
tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
DDR3/DDR3L-1333
Refer to Standard Speed Bins
Min.
0.47
0.47
0.43
0.43
-118
-140
-155
-168
-177
-186
-193
-200
-205
-210
-215
0.38
-500
-255
160
140
400
-80
-70
0.9
0.3
0.4
0.4
0.9
0.3
8
-
-
-
Max.: tCK(avg)max + tJIT(per)max
See table for Data Setup and Hold
tERR(nper)max = (1 + 0.68ln(n)) *
Min.: tCK(avg)min + tJIT(per)min
Note 19
Note 11
Max.
0.53
0.53
160
140
118
140
155
168
177
186
193
200
205
210
215
125
250
250
255
80
70
tJIT(per)max
-
-
-
-
-
-
-
-
-
-
DDR3/DDR3L-1600
Min.
0.47
0.47
0.43
0.43
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
0.38
-450
-225
140
120
360
-70
-60
0.9
0.3
0.4
0.4
0.9
0.3
8
-
-
-
Max.
Note
Note
0.53
0.53
140
120
103
122
136
147
155
163
169
175
180
184
188
100
225
225
225
70
60
19
11
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
Note
Note
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
62
13,19,g
11,13,g
13,14,f
13,14,f
Notes
13,g
d,17
d,17
d,17
13,g
13,g
13,f
25
26
13
28
6