IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 9

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

VDD,VDDQ
CMMAND
IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
2.3 Register Definition
2.3.1 Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by
the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command.
As the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized
and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers
can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even
if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must
be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which
means these commands can be executed any time after power-up without affecting the array contents The mode register
set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time
required between two MRS commands shown as below.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
CK,CK#
RESET#
Note1. From time point “Td” until “Tk” NOP or DES commands must be
applied between MRS and ZQCL commands.
CKE
ODT
RTT
BA
Ta
T=100nS
Tmin=10nS
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Tb
Tc
T=500µS
tCKSRX
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Figure2.1.2 Reset Procedure at Power Stable Condition
tIS
tIS
tIS
Td
1)
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
tXPR
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MRD
MR2
Te
tMRD
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MRD
MR3
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tMRD
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MR1
MRD
Tg
tMRD
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MRD
MR0
Th
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tMOD
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Time
Break
ZQCL
tDLLK
Ti
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tZQinit
Tj
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DON’T
CARE
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tIS
Valid
Valid
Valid
Valid
Tk
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