SSTUA32864EC/G,518 NXP Semiconductors, SSTUA32864EC/G,518 Datasheet - Page 10

• Manufacturer Part Number: SSTUA32864EC/G,518
• Description: IC REG BUFFER 25BIT 96-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUA32864EC/G,518

• Logic Type: 1:1, 1:2 Configurable Registered Buffer
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-LFBGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Package Type: LFBGA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 2V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3538-2; 935279443518; SSTUA32864EC/G-T

NXP Semiconductors
Table 7.
Recommended operating conditions; T
See
[1]
[2]
[3]
Table 8.
Recommended operating conditions; T
Class I, V
[1]
[2]
Table 9.
Recommended operating conditions; V
SSTUA32864_2
Product data sheet
Symbol
f
t
t
t
t
t
Symbol
f
t
t
t
Symbol
dV/dt_r
dV/dt_f
dV/dt_
clock
W
ACT
INACT
su
h
max
PDM
PDMSS
PHL
This parameter is not necessarily production tested.
Data inputs must be active below a minimum time of t
Data and clock inputs must be held at valid levels (not floating) a minimum time of t
Includes 350 ps of test-load transmission line delay.
This parameter is not necessarily production tested.
Figure 6
ref
Timing requirements
Switching characteristics
Output edge rates
= V
Parameter
clock frequency
pulse width
differential inputs active time
differential inputs inactive time
set-up time
hold time
through
Parameter
maximum input clock frequency
peak propagation delay
simultaneous switching peak
propagation delay
HIGH-to-LOW propagation delay
Parameter
rising edge slew rate
falling edge slew rate
absolute difference between dV/dt_r
and dV/dt_f
T
= V
DD
Figure
0.5 and C
11.
L
= 10 pF; unless otherwise specified. See
amb
amb
DD
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
= 1.8 V
= 0 C to +70 C; V
= 0 C to +70 C; V
Conditions
CK, CK HIGH or LOW
DCS before CK , CK , CSR HIGH
DCS before CK , CK , CSR LOW
CSR, ODT, CKE, and data before
CK , CK
DCS, CSR, ODT, CKE, and data
after CK , CK
Rev. 02 — 9 March 2007
Conditions
CK and CK to output
CK and CK to output
RESET to output
0.1 V; unless otherwise specified.
Conditions
ACT(max)
after RESET is taken HIGH.
DD
DD
= 1.8 V
= 1.8 V
0.1 V; unless otherwise specified.
0.1 V;
INACT(max)
Figure 6
[1][2]
[1]
[1][2]
[1][3]
after RESET is taken LOW.
Min
450
1.2
-
-
Min
1
1
-
through
Min
-
1
-
-
0.7
0.5
0.5
0.5
SSTUA32864
Figure
Typ
-
-
-
-
Typ
-
-
-
Typ
-
-
-
-
-
-
-
-
11.
© NXP B.V. 2007. All rights reserved.
Max
-
1.8
2.0
3
Max
4
4
1
Max
450
-
10
15
-
-
-
-
Unit
MHz
ns
ns
ns
Unit
V/ns
V/ns
V/ns
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
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