SSTUB32868ET/G,518 NXP Semiconductors, SSTUB32868ET/G,518 Datasheet - Page 21

IC REG BUFFER CONFIG 176TFBGA

SSTUB32868ET/G,518

Manufacturer Part Number
SSTUB32868ET/G,518
Description
IC REG BUFFER CONFIG 176TFBGA
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SSTUB32868ET/G,518

Package / Case
176-TFBGA
Mounting Type
Surface Mount
Supply Voltage
1.7 V ~ 2 V
Operating Temperature
0°C ~ 70°C
Logic Type
1:2 Configurable Registered Buffer with Parity
Number Of Bits
28
Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Inputs
28
Number Of Outputs
56
High Level Output Current
-8mA
Low Level Output Current
8mA
Propagation Delay Time
1.5ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
2V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Invert/Non-Invert
Technology
CMOS
Frequency (max)
450(Min)MHz
Mounting
Surface Mount
Pin Count
176
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935282727518::SSTUB32868ET/G-T::SSTUB32868ET/G-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SSTUB32868ET/G,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SSTUB32868_4
Product data sheet
11.2 Data output slew rate measurement
V
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z
Fig 15. Load circuit, HIGH-to-LOW slew measurement
Fig 16. Voltage waveforms, HIGH-to-LOW slew rate measurement
Fig 17. Load circuit, LOW-to-HIGH slew measurement
Fig 18. Voltage waveforms, LOW-to-HIGH slew rate measurement
DD
= 1.8 V ± 0.1 V.
(1) C
(1) C
L
L
includes probe and jig capacitance.
includes probe and jig capacitance.
output
All information provided in this document is subject to legal disclaimers.
output
0
= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
Rev. 04 — 22 April 2010
dv_r
1.8 V DDR2-800 configurable registered buffer with parity
dv_f
DUT
DUT
OUT
OUT
C
20 %
L
dt_r
= 10 pF
C
L
(1)
80 %
dt_f
80 %
= 10 pF
(1)
20 %
V
DD
R
test point
test point
R
002aaa377
002aaa379
L
L
= 50 Ω
= 50 Ω
SSTUB32868
002aaa380
002aaa378
V
V
V
V
© NXP B.V. 2010. All rights reserved.
OL
OH
OL
OH
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