SSTUM32866EC/S,518 NXP Semiconductors, SSTUM32866EC/S,518 Datasheet - Page 20

• Manufacturer Part Number: SSTUM32866EC/S,518
• Description: IC BUFFER 1.8V 25BIT 96-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUM32866EC/S,518

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 96-LFBGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Package Type: LFBGA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 2V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935284578518; SSTUM32866EC/S-T; SSTUM32866EC/S-T

NXP Semiconductors
SSTUM32866_1
Product data sheet
11.3 Error output load circuit and voltage measurement information
V
All input pulses are supplied by generators having the following characteristics:
PRR
Fig 20. Load circuit, error output measurements
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
Fig 22. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect
DD
= 1.8 V
(1) C
10 MHz; Z
RESET input.
to clock inputs
L
includes probe and jig capacitance.
0.1 V.
o
waveform 1
= 50 ; input slew rate = 1 V/ns
waveform 2
RESET
output
timing
inputs
output
Rev. 01 — 29 June 2007
LVCMOS
1.8 V DDR2-1G configurable registered buffer with parity
t
DUT
PLH
OUT
V
t
HL
0.5V
ICR
0.15 V
DD
0.5V
DD
C
L
= 10 pF
V
ICR
(1)
20 %, unless otherwise specified.
V
DD
R
test point
002aaa500
L
002aaa502
= 1 k
SSTUM32866
002aaa501
V
V
V
V
0 V
V
0 V
DD
OL
i(p-p)
DD
OH
© NXP B.V. 2007. All rights reserved.
20 of 28