SSTUA32866EC/G,551 NXP Semiconductors, SSTUA32866EC/G,551 Datasheet - Page 9

• Manufacturer Part Number: SSTUA32866EC/G,551
• Description: IC BUFFER 1.8V 25BIT SOT536-1
• Manufacturer: NXP Semiconductors

Specifications of SSTUA32866EC/G,551

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279442551; SSTUA32866EC/G-S; SSTUA32866EC/G-S

NXP Semiconductors
Table 3.
L = LOW voltage level; H = HIGH voltage level; X = don’t care;
[1]
Table 4.
L = LOW voltage level; H = HIGH voltage level; X = don’t care;
[1]
[2]
[3]
[4]
SSTUA32866_2
Product data sheet
RESET
RESET
Q
H
H
H
H
H
H
H
H
H
H
PPO
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
L
H
H
H
H
H
H
H
H
H
H
H
H
L
0
is the previous state of the associated output.
0
is the previous state of output PPO; QERR
Function table (each flip-flop)
Parity and standby function table
X or floating X or floating X or floating X or floating
X or floating
DCS
DCS
H
H
H
H
H
X
L
L
L
L
7.1 Function table
H
H
H
H
H
H
L
L
L
L
L
L
X or floating
CSR
CSR
X
X
X
X
H
X
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
Inputs
X or floating
L or H
CK
L or H
L or H
L or H
L or H
Inputs
CK
0
is the previous state of output QERR.
Rev. 02 — 26 March 2007
1.8 V DDR2-667 configurable registered buffer with parity
X or floating
L or H
CK
L or H
L or H
L or H
L or H
CK
= LOW-to-HIGH transition;
= LOW-to-HIGH transition;
(D1 to D25)
X or floating
of inputs = H
Dn, DODTn,
X or floating
DCKEn
even
even
even
even
odd
odd
odd
odd
X
X
H
X
H
X
H
X
H
X
L
L
L
L
X or floating
PAR_IN
Qn
Q
Q
Q
Q
Q
Q
H
H
H
L
L
L
L
0
0
0
0
0
0
H
H
H
H
X
X
L
L
L
L
SSTUA32866
= HIGH-to-LOW transition
= HIGH-to-LOW transition
[2]
Outputs
QCS
PPO
PPO
PPO
Q
Q
Q
Q
© NXP B.V. 2007. All rights reserved.
H
H
H
H
L
L
L
L
L
0
0
0
0
H
H
H
H
L
L
L
L
L
Outputs
[3]
0
0
[1]
QERR
QODT,
QERR
QERR
QCKE
[1]
Q
Q
Q
Q
H
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
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0
0
0
0
[4]
0
0