IS43DR32800A-37CBL-TR ISSI, IS43DR32800A-37CBL-TR Datasheet - Page 16

• Manufacturer Part Number: IS43DR32800A-37CBL-TR
• Description: DRAM 256M (8Mx32) 266MHz Commercial Temp
• Manufacturer: ISSI

Specifications of IS43DR32800A-37CBL-TR

• Product Category: DRAM
• Rohs: yes
• Factory Pack Quantity: 1500

IS43DR32800A, IS43/46DR32801A
Timing Parameters by Speed Grade (DDR2-400 and DDR2-533)
(For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.)
16
Parameter
Clock cycle time, CL=x
CK HIGH pulse width
CK LOW pulse width
DQS latching rising transitions to associated clock edges
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input HIGH pulse width
DQS input LOW pulse width
Write preamble
Write postamble
Address and control input setup time
Address and control input hold time
Address and control input setup time
Address and control input hold time
Control & Address input pulse width for each input
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input setup time (differential strobe)
DQ and DM input hold time (differential strobe)
DQ and DM input setup time (single-ended strobe)
DQ and DM input hold time (single-ended strobe)
DQ and DM input pulse width for each input
DQ output access time from CK/CK
DQS output access time from CK/ CK
Data-out high-impedance time from CK/ CK
DQS(DQS) low-impedance time from CK/ CK
DQ low-impedance time from CK/ CK
DQS-DQ skew for DQS and associated DQ signals
CK half pulse width
DQ hold skew factor
DQ/DQS output hold time from DQS
Read preamble
Read postamble
tDH1(base)
tDS1(base)
tDS(base)
tDH(base)
tLZ(DQS)
tIS(base)
tIH(base)
Symbol
tDQSCK
tLZ(DQ)
tDQSH
tWPRE
tWPST
tDQSQ
tDQSS
tRPRE
tDQSL
tDIPW
tRPST
tQHS
tDSS
tDSH
tDHa
tIPW
tDSa
tIHa
tCH
tISa
tHP
tQH
tCK
tCL
tAC
tHZ
2 x tAC min tAC max 2 x tAC min tAC max
tHP - tQHS
min (tCL,
tAC min
- 0.25
- 600
- 500
Min.
tCH)
0.45
0.45
0.35
0.35
0.35
0.35
600
600
350
475
400
400
150
275
0.6
0.9
0.4
0.2
0.2
0.4
25
25
5
–
–
–
Integrated Silicon Solution, Inc. — www.issi.com
DDR2-400
tAC max
tAC max
+ 600
+ 500
Max.
0.55
0.55
0.25
350
450
0.6
1.1
0.6
8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
tHP - tQHS
min (tCL,
tAC min tAC max
- 0.25
- 500
- 450
Min.
tCH)
3.75
0.45
0.45
0.35
0.35
0.35
0.35
- 25
- 25
500
500
250
375
350
350
100
225
0.9
0.4
0.2
0.2
0.4
0.6
DDR2-533
–
–
–
tAC max
+ 500
+ 450
Max
0.55
0.55
0.25
300
400
0.6
1.1
0.6
8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Units Notes
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
15
10
5, 7, 9, 22,
29
5, 7, 9, 23,
29
5, 7, 9, 22,
29
5, 7, 9, 23,
29
6, 7, 8, 20,
28, 31
6, 7, 8, 21,
28, 31
6, 7, 8, 20,
28, 31
6, 7, 8, 21,
28, 31
6, 7, 8, 25
6, 7, 8, 26
18
18
18
13
11,12
12
19
19
09/08/2010
Rev. 00E