IS43DR32800A-37CBL-TR ISSI, IS43DR32800A-37CBL-TR Datasheet - Page 34

• Manufacturer Part Number: IS43DR32800A-37CBL-TR
• Description: DRAM 256M (8Mx32) 266MHz Commercial Temp
• Manufacturer: ISSI

Specifications of IS43DR32800A-37CBL-TR

• Product Category: DRAM
• Rohs: yes
• Factory Pack Quantity: 1500

IS43DR32800A, IS43/46DR32801A
Extended Mode Register 2 (EMR2)
The EMR(2) controls refresh related features. The default value of the EMR(2) is not defined, therefore the EMR(2)
must be programmed during initialization for proper operation. The EMR(2) is written by asserting LOW on CS, RAS,
CAS, WE, HIGH on BA1 and LOW on BA0, while controlling the states of address pins A0 - A11/A12. The DDR2
SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the EMR(2). The mode
register set command cycle time (tMRD) must be satisfied to complete the write operation to the EMR(2). Mode
register contents can be changed using the same command and clock cycle requirements during normal operation as
long as all banks are in the precharge state.
EMR(2)
Notes:
1. A3-A6, A8-A12 are reserved for future use and must be set to 0 when programming the EMR(2).
2. If the high temperature self-refresh mods is supported then controller can set the EMR (2) [A7] bit to enable the self-refresh rate if Tc > 85
3. If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self refresh
Extended Mode Register 3 (EMR3)
There is not an EMR(3) defined. It is not necessary to issue an EMRS command to this register (High on BA1 and
BA0), and no effect results.
34
Address
while in self-refresh operation. T
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued.
Field
A12
A11
A10
BA1
BA0
A3*
A9
A8
A6
A5*
A4*
A2
A1
A0
A7
*1
*1
*1
*1
*1
*1
1
1
1
Register
PASR
Mode
SRF
1
0
0
0
0
0
0
0
0
0
0
*3
oper
may not be violated.
A7
A2
0
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
High Temperature Self-Refresh Rate Enable
A0
0
1
0
1
0
1
0
1
Integrated Silicon Solution, Inc. — www.issi.com
Partial Array Self Refresh for 4 Banks
Enable
Disable
*2
Full Array
Reserved
1/4 array
3/4 array
1/2 array
1/4 Array
Reserved
1/2 Array
00,01,10,11
01,10,11
BA [1:0]
10,11
00,01
00
11
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09/08/2010
Rev. 00E
o
C