IS43DR32800A-37CBL-TR ISSI, IS43DR32800A-37CBL-TR Datasheet - Page 2

• Manufacturer Part Number: IS43DR32800A-37CBL-TR
• Description: DRAM 256M (8Mx32) 266MHz Commercial Temp
• Manufacturer: ISSI

Specifications of IS43DR32800A-37CBL-TR

• Product Category: DRAM
• Rohs: yes
• Factory Pack Quantity: 1500

IS43DR32800A, IS43/46DR32801A
GENERAL DESCRIPTION
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue
for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the active
command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A11/A12 select the
row and A0-A7/A8 select the column). The address bits registered coincident with the Read or Write command are
used to select the starting column location for the burst access and to determine if the auto precharge command is
to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed
information covering device initialization, register definition, command descriptions and device operation.
FUNCTIONAL BLOCK DIAGRAM
2
ODT
CKE
RAS
CAS
WE
CK
CK
CS
BA0 – BA1
A0 – An,
Notes:
1.) An: n = no. of address pins – 1
GENERATOR
COMMAND
DECODER
CLOCK
&
ADDRESS
LATCH
ROW
REGISTERS
COLUMN ADDRESS
MODE
BURST COUNTER
ADDRESS LATCH
COLUMN
BUFFER
CONTROLLER
ADDRESS
BUFFER
COUNTER
REFRESH
REFRESH
CONTROLLER
ROW
REFRESH
SELF
BANK CONTROL LOGIC
Integrated Silicon Solution, Inc. — www.issi.com
COLUMN DECODER
MEMORY CELL
MASK LOGIC
COLUMN DECODER
SENSE AMP
I/O GATE
COLUMN DECODER
BANK 0
ARRAY
COLUMN DECODER
MEMORY CELL
&
SENSE AMP
ARRAY
BANK 0
DLL
GENERATOR
OUTPUT
BUFFER
STROBE
DATA
DATA
ODT CIRCUIT
BUFFER
INPUT
DATA
DQ0 – DQ31
DQS0 – DQS3,
DQS0 – DQS3
DM0 – DM3
09/08/2010
Rev. 00E