S9S12G96F0CLL Freescale Semiconductor, S9S12G96F0CLL Datasheet - Page 657
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S9S12G96F0CLL
Manufacturer Part Number
S9S12G96F0CLL
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G96F0CLL
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Available stocks
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Part Number:
S9S12G96F0CLL
Manufacturer:
Freescale Semiconductor
Quantity:
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Each channel counter can be read at anytime without affecting the count or the operation of the PWM
channel.
Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up,
the immediate load of both duty and period registers with values from the buffers, and the output to change
according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When a
channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the
PWMCNTx register. This allows the waveform to continue where it left off when the channel is
re-enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset
on the next selected clock.
Generally, writes to the counter are done prior to enabling a channel in order to start from a known state.
However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is
similar to writing the counter when the channel is disabled, except that the new period is started
immediately with the output set according to the polarity bit.
The counter is cleared at the end of the effective period (see
Section 19.4.2.6, “Center Aligned Outputs”
19.4.2.5
The PWM timer provides the choice of two types of outputs, left aligned or center aligned. They are
selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the
corresponding PWM output will be left aligned.
In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two
registers, a duty register and a period register as shown in the block diagram in
PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to
also change state. A match between the PWM counter and the period register resets the counter and the
output flip-flop, as shown in
duty register to the associated registers, as described in
counter counts from 0 to the value in the period register – 1.
Freescale Semiconductor
When PWMCNTx register written to
Counter Clears ($00)
Effective period ends
any value
Left Aligned Outputs
If the user wants to start a new “clean” PWM waveform without any
“history” from the old waveform, the user must write to channel counter
(PWMCNTx) prior to enabling the PWM channel (PWMEx = 1).
Writing to the counter while the channel is enabled can cause an irregular
PWM cycle to occur.
Figure
Table 19-12. PWM Timer Counter Conditions
MC9S12G Family Reference Manual, Rev.1.23
19-16, as well as performing a load from the double buffer period and
(PWMEx = 1). Counts from last value in
When PWM channel is enabled
for more details).
Counter Counts
PWMCNTx.
NOTE
NOTE
Section 19.4.2.3, “PWM Period and
Section 19.4.2.5, “Left Aligned Outputs”
Pulse-Width Modulator (S12PWM8B8CV2)
When PWM channel is disabled
Figure
Counter Stops
(PWMEx = 0)
19-16. When the
Duty”. The
and
659
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