ispLSI 1016E-100LJN Lattice, ispLSI 1016E-100LJN Datasheet - Page 2
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ispLSI 1016E-100LJN
Manufacturer Part Number
ispLSI 1016E-100LJN
Description
CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
Manufacturer
Lattice
Datasheet
1.ISPLSI_1016E-100LT44.pdf
(17 pages)
Specifications of ispLSI 1016E-100LJN
Rohs
yes
Memory Type
EEPROM
Number Of Macrocells
64
Maximum Operating Frequency
125 MHz
Delay Time
13 ns
Number Of Programmable I/os
32
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
PLCC-44
Mounting Style
SMD/SMT
Factory Pack Quantity
780
Supply Current
90 mA
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
• HIGH-DENSITY PROGRAMMABLE LOGIC
• HIGH PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• COMBINES EASE OF USE AND THE FAST SYSTEM
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1016_10
Features
— High-Speed Global Interconnect
— 2000 PLD Gates
— 32 I/O Pins, Four Dedicated Inputs
— 96 Registers
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— Security Cell Prevents Unauthorized Copying
—
—
—
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E
— 100% Tested
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Debugging
SPEED OF PLDs WITH THE DENSITY AND FLEX-
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
f
f
t
Market, and Improved Product Quality
Machines, Address Decoders, etc.
Logic and Structured Designs
Interconnectivity
max = 110 MHz Maximum Operating Frequency
max = 60 MHz for Industrial and Military/883 Devices
pd = 10 ns Propagation Delay
2
CMOS Technology
2
CMOS
®
TECHNOLOGY
1
The ispLSI 1016 is a High-Density Programmable Logic
Device containing 96 Registers, 32 Universal I/O pins,
four Dedicated Input pins, three Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP pro-
vides complete interconnectivity between all of these
elements. The ispLSI 1016 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1016 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. B7 (see figure 1). There are a total of 16 GLBs in the
ispLSI 1016 device. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Functional Block Diagram
Description
In-System Programmable High Density PLD
A1
A2
A3
A4
A5
A6
A7
A0
Global Routing Pool (GRP)
ispLSI
Logic
Array
D Q
D Q
D Q
D Q
GLB
®
January 2002
1016
B 7
B 6
B 5
B 4
B 3
B 2
B 1
B 0
CLK