MAX11359AETL Maxim Integrated, MAX11359AETL Datasheet - Page 12

• Manufacturer Part Number: MAX11359AETL
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11359AETL

• Number Of Channels: 10
• Architecture: Sigma-Delta
• Conversion Rate: 10 SPs to 512 SPs
• Resolution: 16 bit
• Input Type: Differential
• Interface Type: 4-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Power Dissipation: 2051.3 mW
• Number Of Converters: 1
• Voltage Reference: 1.251 V 1.996 V, 2.422 V

16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
TIMING CHARACTERISTICS (Figures 1 and 20)
(V
10µF between CF+ and CF-, T
MAX11359A
12
Note 16: The delay for the sleep voltage monitor output, RESET, to go high after V
Note 17: It is gated by an AND function with three inputs—the external RESET signal, the internal DV
Note 18: If FLLE = 0, the internal signal CRDY is not generated by the FLL block and INT or INT are deasserted.
Note 19: CRDY is used as an interrupt signal to inform the µC that the high-frequency clock has started. Only valid if FLLE = 1.
Note 20: t
Note 21: t
SCLK Operating Frequency
SCLK Cycle Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to DOUT Valid
CS Fall to Output Enable
CS Rise to DOUT Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
DVDD Monitor Timeout Period
Wake-Up (WU) Pulse Width
Shutdown Delay
HFCK Turn-On Time
CRDY to INT Delay
HFCK Disable Delay
SHDN Assertion Delay
AVDD
= V
driven by the startup of the 32kHz oscillator.
external SHDN signal. The time delay is timed from the internal LOV
whichever happens later. HFCK always starts in the low state.
PARAMETER
DFOF
DPD
AVDD
is greater than the HFCK delay for the MAX11358B/MAX11359A to clean up before losing power.
gives the µC time to clean up and go into sleep-override mode properly.
= +1.8V to +3.6V, external V
A
= T
MIN
SYMBOL
t
f
t
to T
t
DFON
t
t
t
t
SCLK
t
DSLP
DFOF
t
t
t
CYC
t
t
CSH
DPU
DPD
t
t
t
t
CSS
DO
WU
DFI
CH
DH
CL
DS
DV
TR
MAX
REF
, unless otherwise noted. Typical values are at T
C
C
C
(Note 16)
Minimum pulse width required to detect a
wake-up event
The delay for SHDN to go high after a valid
wake-up event
The turn-on time for the high-frequency
clock and FLL (FLLE = 1) (Note 17)
If FLLE = 0, the turn-on time for the high-
frequency clock (Note 18)
The delay for CRDY to go low after the
HFCK clock output has been enabled
(Note 19)
The delay after a shutdown command has
asserted and before HFCK is disabled
(Note 20)
(Note 21)
= +1.25V, CLK32K = 32.768kHz (external clock), C
L
L
L
= 50pF, Figure 2
= 50pF, Figure 2
= 50pF, Figure 2
CONDITIONS
DD
DD
going high or the external RESET going high,
rises above the reset threshold. This is largely
A
= +25°C.) (Note 1)
MIN
100
40
40
30
20
0
0
0
REG
DD
TYP
7.82
1.95
2.93
1.5
= 10µF, C
1
1
monitor output, and the
MAX
10
40
48
48
10
10
Maxim Integrated
CPOUT
UNITS
= 10µF,
MHz
ms
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
s