MAX11359AETL Maxim Integrated, MAX11359AETL Datasheet - Page 40

• Manufacturer Part Number: MAX11359AETL
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11359AETL

• Number Of Channels: 10
• Architecture: Sigma-Delta
• Conversion Rate: 10 SPs to 512 SPs
• Resolution: 16 bit
• Input Type: Differential
• Interface Type: 4-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Power Dissipation: 2051.3 mW
• Number Of Converters: 1
• Voltage Reference: 1.251 V 1.996 V, 2.422 V

AON: ADC and DAC/op-amp power-on bit. This bit pro-
vides a method of turning on several analog functions
with a single write. Setting AON = 1 asserts the ADCE
bit in the ADC register and DAE/OP3E, OP2E, and
OP1E bits in the DACA_OP register, powering up these
blocks. Setting AON = 0 has no effect. The AON bit has
priority when both AON and AOFF bits are asserted.
Most of the analog functions can be enabled with a sin-
gle write to the REF_SDC register using AON,
REFV<1:0>, and SDCE.
SDCE: Signal-detect comparator power-enable bit. Set
SDCE = 1 to power up the signal-detect comparator,
and set SDCE = 0 to power down the signal-detect
comparator. The ADCE bit in the ADC register must be
set to 1 to use the signal-detect comparator.
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
The AL_DAY register stores the second information of
the time-of-day alarm.
ASEC<19:0>: Alarm-second bits. These 20 bits store
the time-of-day alarm, which corresponds to the lower
20 bits of the RTC second counter or SEC<19:0>.
Program the time-of-day alarm trigger between 1s to
just over 12 days beyond the current RTC second
counter value in increments of 1s.
Assert the AWE bit in the CLK_CTRL register (see the
CLK_CTRL Register section) to enable writing to the
AL_DAY register. Enabling the time-of-day alarm requires
two writes to the CLK_CTRL register. Write the 20 alarm-
second bits in 3 bytes, MSB first. If CS is raised before
the LSB is written, the alarm write is aborted, and the
existing value remains. When the lower 20 bits in the RTC
MAX11359A
AL_DAY Register (Power-On State: 0000 0000 0000 0000 0000 XXXX)
40
ASEC19
ASEC11
ASEC3
MSB
ASEC18
ASEC10
ASEC2
ASEC17
ASEC9
ASEC1
ASEC16
ASEC8
ASEC0
TSEL<2:0>: Threshold-select bits. These bits select the
threshold for the signal-detect comparator as shown in
Table 11.
second counter match the contents of this register, the
alarm triggers and asserts ALD in the STATUS register. It
also asserts an interrupt on the INT pin unless masked by
the MALD bit in the IMSK register. The part enters normal
mode if an alarm triggers while in sleep mode. The time-
of-day alarm is intended to trigger single events.
Therefore, once it triggers, in the CLK_CTRL register, the
ADE bit is automatically cleared, disabling the time-of-
day alarm. Implement a recurring alarm with repeated
software writes over the serial interface each time the
time-of-day alarm triggers. The time-of-day alarm can
also be programmed to output at the UPIO pins.
When configured this way the MALD bit does not mask
the UPIO alarm output.
Table 11. Setting the Signal-Detect
Comparator Threshold
X = Don’t care.
THRESHOLD (mV)
ASEC15
ASEC7
X
NOMINAL
100
150
200
50
0
ASEC14
ASEC6
X
TSEL2
0
1
1
1
1
ASEC13
ASEC5
X
TSEL1
X
0
0
1
1
Maxim Integrated
ASEC12
ASEC4
LSB
TSEL0
X
X
0
1
0
1