MAX11359AETL Maxim Integrated, MAX11359AETL Datasheet - Page 29

• Manufacturer Part Number: MAX11359AETL
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11359AETL

• Number Of Channels: 10
• Architecture: Sigma-Delta
• Conversion Rate: 10 SPs to 512 SPs
• Resolution: 16 bit
• Input Type: Differential
• Interface Type: 4-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Power Dissipation: 2051.3 mW
• Number Of Converters: 1
• Voltage Reference: 1.251 V 1.996 V, 2.422 V

Enable the watchdog timer by writing a 1 to the WDE
bit in the CLK_CTRL register. After enabling the watch-
dog timer, the device asserts RESET for 250ms, if the
watchdog address register is not written every 500ms.
Due to the asynchronous nature of the watchdog timer,
the watchdog timeout period varies between 500ms
and 750ms. Write a 0 to the WDE bit to disable the
watchdog timer. See Figure 11 for a block diagram of
the watchdog timer.
An internal oscillator and a frequency-locked loop (FLL)
are used to generate a 4.9152MHz ±1% high-frequen-
cy clock. This clock and derivatives are used internally
by the ADC, analog switches, and PWM. This clock sig-
nal outputs to CLK. When the FLL is enabled, the high-
Figure 9. 32kHz Crystal-Oscillator Block Diagram
Figure 11. Watchdog Timer Block Diagram
Maxim Integrated
UPIOs, RTC, Voltage Monitors, and Temp Sensor
16-Bit Data-Acquisition System with ADC, DAC,
32KOUT
32KIN
32K
POR PULSES HIGH DURING POWER-UP.
WDW PULSES HIGH DURING WATCHDOG REGISTER WRITE.
WDE
High-Frequency Clock
OSCILLATOR
32.768kHz OSCILLATOR
OSCE
32kHz
BY-8192
DIVIDE-
WDW
POR
Watchdog
4Hz
32K
D
CK
R
Q
Q
frequency clock is locked to the 32.768kHz reference.
If the FLL is disabled, the high-frequency clock is free-
running. At power-up, the CLK pin defaults to a
2.4576MHz clock output, which is compatible with most
µCs. See Figure 12 for a block diagram of the high-fre-
quency clock.
The MAX11359A provides four digital programmable
I/Os (UPIO1–UPIO4). Configure UPIOs as logic inputs
or outputs using the UPIO control register. Configure
the internal pullups using the UPIO setup register, if
required. At power-up, the UPIOs are internally pulled
up to DVDD. UPIO_ outputs can be referenced to
DVDD or CPOUT. See the UPIO__CTRL Register and
UPIO_SPI Register sections for more details on config-
uring the UPIO_ pins.
Figure 10. CLK32K I/O Block Diagram
CLK32K
32K
D
CK
R
CK32E
OSCE
IO32E
Q
Q
WATCHDOG TIMER
IO32E
User-Programmable I/Os
MAX11359A
CLK32K I/O CONTROL
WDTO
IO32E
0
1
MUX
2:1
M32K
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