SSTV16859GX Fairchild Semiconductor, SSTV16859GX Datasheet - Page 6

• Manufacturer Part Number: SSTV16859GX
• Description: IC REG 13BIT DUAL SSTL-2 96FBGA
• Manufacturer: Fairchild Semiconductor
• Series: 74SSTVr

Specifications of SSTV16859GX

• Logic Type: Register with SSTL-2 Compatible I/O and Reset
• Supply Voltage: 2.3 V ~ 2.7 V
• Number Of Bits: 13
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-FBGA
• Logic Family: SSTV
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 13
• Number Of Outputs: 26
• High Level Output Current: -20mA
• Low Level Output Current: 20mA
• Package Type: FBGA
• Propagation Delay Time: 5ns
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Output Type: Standard
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 200(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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AC Loading and Waveforms
Note: C
Note: I
FIGURE 5. Voltage Waveforms - Setup and Hold Times
FIGURE 3. Voltage and Current Waveforms Inputs
and I
DD
L
includes probe and jog capacitance
tested with clock and data inputs held at V
O
0 mA.
FIGURE 7. Voltage Waveforms -
RESET Removal Delay Times
FIGURE 1. AC Test Circuit
Active and Inactive Times
DD
or GND,
(See Notes A through F below)
6
Note A: All input pulses are supplied by generators having
the following characteristics:
Note B: The outputs are measured one at a time with one
transition per measurement.
Note C: V
Note D: V
ential inputs. V
Note E: V
ential inputs. V
Note F: Removal time (t
held active HIGH. The propagation time from CK to the cor-
responding output must meet valid timing specifications for
the measurement to be accurate.
PRR
(unless otherwise specified).
FIGURE 2. Voltage Waveforms - Pulse Duration
10 MHz, Z
TT
IL
IH
RESET Propagation Delay Times
FIGURE 4. Voltage Waveforms -
FIGURE 6. Voltage Waveforms -
V
V
V
IH
IL
REF
Propagation Delay Times
REF
REF
GND for LVCMOS input.
V
0
DD
310 mV (AC voltage levels) for differ-
310 mV (AC voltage levels) for differ-
V
50 , input slew rate
for LVCMOS input.
DD
REM
/2.
) is tested with one data input
1V/ns
20%