MM912F634DV1AE Freescale Semiconductor, MM912F634DV1AE Datasheet - Page 226

• Manufacturer Part Number: MM912F634DV1AE
• Description: 16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
• Manufacturer: Freescale Semiconductor

Specifications of MM912F634DV1AE

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 4.5 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

Functional Description and Application Information
4.31.3.2.8.1
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the
DBG module register address map.
Table 289. Debug Comparator Control Register DBGACTL (Comparator A)
Table 290. Debug Comparator Control Register DBGBCTL (Comparator B)
Table 291. Debug Comparator Control Register DBGCCTL (Comparator C)
Read: DBGACTL if COMRV[1:0] = 00
DBGBCTL if COMRV[1:0] = 01
DBGCCTL if COMRV[1:0] = 10
Write: DBGACTL if COMRV[1:0] = 00 and DBG not armed
DBGBCTL if COMRV[1:0] = 01 and DBG not armed
DBGCCTL if COMRV[1:0] = 10 and DBG not armed
Table 292. DBGXCTL Field Descriptions
Freescale Semiconductor
Address: 0x0028
Address: 0x0028
Address: 0x0028
(Comparator B)
(Comparator A)
(Comparator B)
Reset
Reset
Reset
W
W
W
R
R
R
Field
NDB
SZE
SZ
7
6
6
SZE
0
0
0
0
0
7
7
7
Debug Comparator Control Register (DBGXCTL)
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the associated
comparator. This bit is ignored if the TAG bit in the same register is set.
0 Word/Byte access size is not used in comparison
1 Word/Byte access size is used in comparison
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator register value
or when the data bus differs from the register value. This bit is ignored if the TAG bit in the same register is set. This bit is
only available for comparator A.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the associated
comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set. This bit is only featured
in comparator B.
0 Word access size will be compared
1 Byte access size will be compared
NDB
SZ
0
0
0
0
6
6
6
TAG
TAG
TAG
5
0
5
0
5
0
BRK
BRK
BRK
0
0
0
4
4
4
Description
RW
RW
RW
0
0
0
3
3
3
RWE
RWE
RWE
S12S Debug (S12SDBGV1) Module
0
0
0
2
2
2
1
0
0
1
0
0
1
0
0
MM912F634
COMPE
COMPE
COMPE
0
0
0
0
0
0
226