MM912F634DV1AE Freescale Semiconductor, MM912F634DV1AE Datasheet - Page 294

• Manufacturer Part Number: MM912F634DV1AE
• Description: 16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
• Manufacturer: Freescale Semiconductor

Specifications of MM912F634DV1AE

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 4.5 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

Functional Description and Application Information
4.36.4.2.6
The set verify margin level operation, available only in special mode, will set the margin level in the Flash array sense-amps to
allow content validation with margin to the normal level for subsequent Flash array reads. The set verify margin level command
should only be used to validate initial programming of the Flash array.
An example flow to execute the set verify margin level operation is shown in
command write sequence is as follows:
Once the set verify margin level command has successfully launched, the CCIF flag in the FSTAT register will set after the set
verify margin level operation has completed.
Freescale Semiconductor
1.
2.
3.
Write to an aligned Flash block address to start the command write sequence for the set verify margin level command.
The address will be ignored while the data written sets the margin level as shown in
Write the set verify margin level command, 0x75, to the FCMD register.
Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the set verify margin level command.
Table 384. Flash Array Margin Level Settings
Command Data Field
Set Verify Margin Level Command
0x0000
0x0005
0x0024
Margin Level Setting
Margin 0
Margin 1
Normal
Sets test level to validate margin to reading 0’s
Sets test level to validate margin to reading 1’s
Sets normal level for Flash array reads
Description
32 kbyte Flash Module (S12SFTSR32KV1)
Figure
91. The set verify margin level
Table
384.
MM912F634
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