MAX1254AEUE+ Maxim Integrated, MAX1254AEUE+ Datasheet - Page 5

• Manufacturer Part Number: MAX1254AEUE+
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1254AEUE+

• Number Of Channels: 10
• Architecture: SAR
• Conversion Rate: 94 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Interface Type: Serial
• Operating Supply Voltage: 4.5 V to 5.5 V
• Number Of Converters: 1
• Voltage Reference: Internal 4.096 V or External

TIMING CHARACTERISTICS
(V
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain and offset errors
Note 2: Offset nulled.
Note 3: In reference mode 00, the reference system powers up for each temperature measurement. In reference mode 01, the ref-
Note 4: No external capacitor on REF.
Note 5: The operational input voltage range for each individual input of a differentially configured pair (AIN0–AIN7) is from GND to
Note 6: See Figure 3 and the Sampling Error vs. Input Source Impedance graph in the Typical Operating Characteristics section.
Note 7: Grade A tested at +10°C and +55°C. -20°C to +85°C and -40°C to +85°C specifications guaranteed by design. Grade B
Note 8: External temperature measurement mode using an MMBT3904 (Diodes Inc.) as a sensor. External temperature sensing
Note 9: Performing eight single-ended external channels’ temperature measurements, an internal temperature measurement, and
Note 10: Performing eight single-ended voltage measurements, an internal temperature measurement, and an internal V
Note 11: Performing eight single-ended voltage measurements, an internal temperature measurement, and an internal V
Note 12: Defined as the shift in the code boundary as a result of supply voltage change. V
with Internal Temperature Sensor and V
SCLK Clock Period
SCLK Pulse Width High Time
SCLK Pulse Width Low Time
DIN to SCLK Setup Time
DIN to SCLK Hold Time
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Fall to DOUT Valid
CS Rise to DOUT Disable
CS Fall to DOUT Enable
CS Pulse Width High
DD
= +2.7V to +3.6V (MAX1253), V
Stand-Alone, 10-Channel, 12-Bit System Monitors
have been calibrated.
erence system powers up once per sequence of channels scanned. If a sample wait <80µs is programmed, the reference
system is on all the time. In reference mode 10, the reference system is on all the time (see Table 7).
V
tested at +25°C. T
from -40°C to +85°C; MAX1253/MAX1254 held at +25°C.
an internal V
ment with no sample wait results in a conversion rate of 7ksps per channel.
ment with maximum sample wait results in a conversion rate of 3ksps per channel.
sured using external reference.
DD
PARAMETER
. The operational input voltage difference is from -V REF /2 to +V REF /2.
_______________________________________________________________________________________
DD
measurement with no sample wait results in a conversion rate of 2ksps per channel.
MIN
to T
MAX
DD
SYMBOL
= +4.5V to +5.5V (MAX1254), T
specification guaranteed by design.
t
t
t
t
t
t
DOD
CSW
t
t
CSH
DOV
DOE
t
t
t
CSS
CH
DH
CP
CL
DS
C
C
C
L
L
L
= 30pF
= 30pF
= 30pF
CONDITIONS
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Figures 1, 2, and 4)
DD
= min to max; full-scale input, mea-
MIN
100
45
45
25
25
50
40
0
DD
TYP
0.5
Monitor
MAX
50
40
40
DD
DD
measure-
measure-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5