MK20DX128VMP5 Freescale Semiconductor, MK20DX128VMP5 Datasheet - Page 53

• Manufacturer Part Number: MK20DX128VMP5
• Description: ARM Microcontrollers - MCU KINETIS 128K FLEX
• Manufacturer: Freescale Semiconductor

Specifications of MK20DX128VMP5

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: Kinetis K20
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: MAPBGA-64
• Mounting Style: SMD/SMT

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Freescale Semiconductor, Inc.
S11
S12
S13
S14
S15
S16
S17
S18
S19
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Num.
Table 39. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid
voltage range)
S5
S7
Figure 21. I2S/SAI timing — master modes
Characteristic
S4
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
S9
S9
S1
S3
S2
S10
S4
S2
1
S8
1.71
250
45%
30
3
—
0
30
2
—
S7
Peripheral operating requirements and behaviors
Min.
3.6
—
55%
—
—
63
—
—
—
72
Max.
V
ns
MCLK period
ns
ns
ns
ns
ns
ns
ns
Unit
S10
S6
S8
53