SIM3U146-B-GQ Silicon Labs, SIM3U146-B-GQ Datasheet - Page 38

• Manufacturer Part Number: SIM3U146-B-GQ
• Description: ARM Microcontrollers - MCU ARM Cortex-M3 USB 64KB TQFP64
• Manufacturer: Silicon Labs

Specifications of SIM3U146-B-GQ

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SIM3U1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 80 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2 x I2C, I2S, 3 x SPI, 2 x USART, 2 x UART
• Number Of Programmable I/os: 65
• Number Of Timers: 2 x 32 bit
• Supply Voltage - Max: 3.6 V

SiM3U1xx
4.1.5. Device Power Modes
The SiM3U1xx devices feature four low power modes in addition to normal operating mode. Several peripherals
provide wake up sources for these low power modes, including the Low-Power Timer (LPT0), RTC0 (alarms and
oscillator failure notification), Comparator 0, and PMU Pin Wake.
In addition, all peripherals can have their clocks disabled to reduce power consumption whenever a peripheral is
not being used using the clock control (CLKCTRL) registers.
4.1.5.1. Normal Mode (Power Mode 0)
Normal Mode is the default mode of the device. The core and peripherals are fully operational, and instructions are
executed from flash memory.
4.1.5.2. Power Mode 1
In Power Mode 1 the core and peripherals are fully operational, with instructions executing from RAM. Compared
with Normal Mode, the active power consumption of the device in PM1 is reduced. Additionally, at higher speeds in
PM1, the core throughput can also be increased because RAM does not require additional wait states that reduce
the instruction fetch speed.
4.1.5.3. Power Mode 2
In Power Mode 2 the core halts and any enabled peripherals continue to run at the selected clock speed. The
power consumption in PM2 corresponds to the AHB and APB clocks left enabled, thus the power can be tuned to
the optimal level for the needs of the application. To place the device in PM2, the core should execute a wait-for-
interrupt (WFI) or wait-for-event (WFE) instruction. If the WFI instruction is called from an interrupt service routine,
the interrupt that wakes the device from PM2 must be of a sufficient priority to be recognized by the core. It is
recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction Syncronization
Barrier) operation prior to the WFI to ensure all bus accesses complete. When operating from the LFOSC0 with
the DMACTRL0 AHB clock disabled, PM2 can achieve similar power consumption to PM3, but with the ability to
wake on APB-clocked interrupts. For example, enabling only the APB clock to the Ports will allow the firmware to
wake on a PMATCH0, PBEXT0 or PBEXT1 interrupt with minimal impact on the supply current.
4.1.5.4. Power Mode 3
In Power Mode 3, the AHB and APB clocks are halted. The device may only wake from enabled interrupt sources
which do not require the APB clock (RTC0ALRM, RTC0FAIL, LPTIMER0, VDDLOW and VREGLOW). A special
fast wake option allows the device to operate at a very low level from the RTC0TCLK or LFOSC0 oscillator while in
PM3, but quickly switch to the faster LPOSC0 when the wake event occurs. Because the current consumption of
these blocks is minimal, it is recommended to use the fast wake option.
The device will enter PM3 on a WFI or WFE instruction. Because all AHB master clocks are disabled, the LPOSC
will automatically halt and go into a low-power suspended state. If the WFI instruction is called from an interrupt
service routine, the interrupt that wakes the device from PM3 must be of a sufficient priority to be recognized by the
core. It is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction
Synchronization Barrier) operation prior to the WFI to ensure all bus access is complete.
4.1.5.5. Power Mode 9
In Power Mode 9, the core and all peripherals are halted, all clocks are stopped, and the pins and peripherals are
set to a lower power mode. In addition, standard RAM contents are not preserved, though retention RAM contents
are still available after exiting the power mode. This mode provides the lowest power consumption for the device,
but requires an appropriate reset to exit. The available reset sources to wake from PM9 are controlled by the
Power Management Unit (PMU).
Before entering PM9, the desired reset source(s) should be configured in the PMU. The SLEEPDEEP bit in the
ARM System Control Register should be set, and the PMSEL bit in the RSTSRC0_CONFIG register must be set to
indicate that PM9 is the desired power mode.
The device will enter PM9 on a WFI or WFE instruction, and remain in PM9 until a reset configured by the PMU
occurs. It is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction
Synchronization Barrier) operation prior to the WFI to ensure all bus access is complete.
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