SIM3U146-B-GQ Silicon Labs, SIM3U146-B-GQ Datasheet - Page 45

• Manufacturer Part Number: SIM3U146-B-GQ
• Description: ARM Microcontrollers - MCU ARM Cortex-M3 USB 64KB TQFP64
• Manufacturer: Silicon Labs

Specifications of SIM3U146-B-GQ

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SIM3U1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 80 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2 x I2C, I2S, 3 x SPI, 2 x USART, 2 x UART
• Number Of Programmable I/os: 65
• Number Of Timers: 2 x 32 bit
• Supply Voltage - Max: 3.6 V

4.6. Communications Peripherals
4.6.1. External Memory Interface (EMIF0)
The External Memory Interface (EMIF0) allows external parallel asynchronous devices, like SRAMs and LCD
controllers, to appear as part of the system memory map. The EMIF0 module includes the following features:
4.6.2. USB0
The USB0 module has complete Full/Low Speed USB function for USB peripheral implementations. The USB
Function Controller (USBn) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching
resistors and configurable pull-up resistors), 2k FIFO block, and dedicated USBn oscillator with clock recovery
mechanism for crystal-less operation. No external components are required. The USB Function Controller and
Transceiver is Universal Serial Bus Specification 2.0 compliant.
The USB0 module includes the following features:
4.6.3. USART (USART0, USART1)
The USART uses two signals (TX and RX) and a predetermined fixed baud rate to communicate with a single
device. In addition to these signals, the USART0 module can optionally use a clock (UCLK) or hardware
handshaking (RTS and CTS).
The USART module provides the following features:
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Provides a memory mapped view of multiple external devices.
Support for byte, half-word and word accesses regardless of external device data-width.
Error indicator for certain invalid transfers.
Minimum external timing allows for 3 clocks per write or 4 clocks per read.
Output bus can be shared between non-muxed and muxed devices.
Available extended address output allows for up to 24-bit address with 8-bit parallel devices.
Support for 8-bit and 16-bit (muxed-mode only) devices with up to two chip-select signals.
Support for internally muxed devices with dynamic address shifting.
Fully programmable control signal waveforms.
Full and Low Speed functionality.
Implements 5 bidirectional endpoints, with 4 of these capable of initiating autonomous DMA transfers.
USB 2.0 compliant USB peripheral support (no host capability).
Direct module access to 2k bytes of RAM for dedicated FIFO memory.
Dedicated USB0 oscillator with clock recovery to meet USB clocking requirements with no external
components.
Additional clocking options include PLL or external oscillator outputs.
Independent transmitter and receiver configurations with separate 16-bit baud rate generators.
Synchronous or asynchronous transmissions and receptions.
Clock master or slave operation with programmable polarity and edge controls.
Up to 5 Mbaud (synchronous or asynchronous, TX or RX, and master or slave) or 1 Mbaud Smartcard (TX
or RX).
Individual enables for generated clocks during start, stop, and idle states.
Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads
and writes.
Data bit lengths from 5 to 9 bits.
Programmable inter-packet transmit delays.
Auto-baud detection with support for the LIN SYNC byte.
Automatic parity generation (with enable).
Automatic start and stop generation (with separate enables).
Transmit and receive hardware flow-control.
Independent inversion correction for TX, RX, RTS, and CTS signals.
Rev. 1.0
SiM3U1xx
45