SIM3U146-B-GQ Silicon Labs, SIM3U146-B-GQ Datasheet - Page 47

• Manufacturer Part Number: SIM3U146-B-GQ
• Description: ARM Microcontrollers - MCU ARM Cortex-M3 USB 64KB TQFP64
• Manufacturer: Silicon Labs

Specifications of SIM3U146-B-GQ

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SIM3U1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 80 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2 x I2C, I2S, 3 x SPI, 2 x USART, 2 x UART
• Number Of Programmable I/os: 65
• Number Of Timers: 2 x 32 bit
• Supply Voltage - Max: 3.6 V

provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and start/
stop control and generation.
The I2C module includes the following features:
4.6.7. I
The I
justified, or time domain multiplexing format, de-serializes the data, and generates requests to transfer the data
using the DMA. The module also reads stereo audio samples from the DMA, serializes the data, and sends it out of
the chip on a data line in the same standard serial format for digital audio. The I
signals: SCK (bit clock), WS (word select or frame sync), and SD (data input). The block’s transmit interface
consists of 3 signals: SCK (bit clock), WS (word select or frame sync) and SD (data output).
The I
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2
2
S module receives digital data from an external source over a data line in the standard I
S module includes the following features:
2
S (I2S0)
Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.
Can operate down to APB clock divided by 32768 or up to APB clock divided by 8.
Support for master, slave, and multi-master modes.
Hardware synchronization and arbitration for multi-master mode.
Clock low extending (clock stretching) to interface with faster masters.
Hardware support for 7-bit slave and general call address recognition.
Firmware support for 10-bit slave address decoding.
Ability to disable all slave states.
Programmable clock high and low period.
Programmable data setup/hold times.
Spike suppression up to 2 times the APB period.
Master or slave capability.
Flexible 10-bit clock divider with 8-bit fractional clock divider provides support for various common
sampling frequencies (16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz) for up to two 32-bit
channels.
Support for DMA data transfers.
Support for various data formats.
Time Division Multiplexing
Rev. 1.0
2
S receive interface consists of 3
SiM3U1xx
2
S, left-justified, right-
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