LPC1111FHN33/203,5 NXP Semiconductors, LPC1111FHN33/203,5 Datasheet - Page 447
LPC1111FHN33/203,5
Manufacturer Part Number
LPC1111FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 8kB flash up to 4 kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1111FHN33/203,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1111
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
8 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Interface Type
I2C, SPI, UART
Number Of Programmable I/os
42
Number Of Timers
4
Program Memory Type
Flash
Factory Pack Quantity
260
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UM10398
User manual
28.4.1.3.1 General-purpose registers
28.4.1.3.2 Stack Pointer
Table 419. Core register set summary
[1]
[2]
R0-R12 are 32-bit general-purpose registers for data operations.
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register
indicates the stack pointer to use:
Name
R0-R12
MSP
PSP
LR
PC
PSR
APSR
IPSR
EPSR
PRIMASK
CONTROL
Fig 95. Processor core register set
•
•
Describes access type during program execution in thread mode and Handler mode. Debug access can
differ.
Bit[24] is the T-bit and is loaded from bit[0] of the reset vector.
0 = Main Stack Pointer (MSP). This is the reset value.
1 = Process Stack Pointer (PSP).
Type
RW
RW
RW
RW
RW
RW
RW
RO
RO
RW
RW
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
[1]
Rev. 12 — 24 September 2012
Reset value
Unknown
See description
Unknown
Unknown
See description
Unknown
Unknown
0x00000000
Unknown
0x00000000
0x00000000
[2]
[2]
Description
Section 28–28.4.1.3.1
Section 28–28.4.1.3.2
Section 28–28.4.1.3.2
Section 28–28.4.1.3.3
Section 28–28.4.1.3.4
Table 28–420
Table 28–421
Table 422
Table 28–423
Table 28–424
Table 28–425
UM10398
© NXP B.V. 2012. All rights reserved.
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