LPC1111FHN33/203,5 NXP Semiconductors, LPC1111FHN33/203,5 Datasheet - Page 488
LPC1111FHN33/203,5
Manufacturer Part Number
LPC1111FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 8kB flash up to 4 kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1111FHN33/203,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1111
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
8 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Interface Type
I2C, SPI, UART
Number Of Programmable I/os
42
Number Of Timers
4
Program Memory Type
Flash
Factory Pack Quantity
260
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NXP Semiconductors
UM10398
User manual
28.5.6.1.1 Syntax
28.5.6.1.2 Operation
28.5.6.1.3 Restrictions
28.5.6.1 B, BL, BX, and BLX
Table 436. Branch and control instructions
Branch instructions.
B{cond} label
BL label
BX Rm
BLX Rm
where:
All these instructions cause a branch to the address indicated by label or contained in the
register specified by Rm. In addition:
BL and BLX instructions also set bit[0] of the LR to 1. This ensures that the value is
suitable for use by a subsequent POP {PC} or BX instruction to perform a successful
return branch.
Table 437
Table 437. Branch ranges
In these instructions:
Mnemonic
BL
BLX
BX
Instruction
B label
Bcond label
BL label
BX Rm
BLX Rm
•
•
•
cond is an optional condition code, see
label is a PC-relative expression. See
Rm is a register providing the address to branch to.
The BL and BLX instructions write the address of the next instruction to LR, the link
register R14.
The BX and BLX instructions result in a HardFault exception if bit[0] of Rm is 0.
Do not use SP or PC in the BX or BLX instruction.
shows the ranges for the various branch instructions.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Brief description
Branch with Link
Branch indirect with Link
Branch indirect
Rev. 12 — 24 September 2012
Section
Section
Branch range
2 KB to +2 KB
256 bytes to +254 bytes
16 MB to +16 MB
Any value in register
Any value in register
See
Section 28–28.5.6.1
Section 28–28.5.6.1
Section 28–28.5.6.1
28–28.5.3.5.
28–28.5.3.6.
UM10398
© NXP B.V. 2012. All rights reserved.
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