MK30DN512ZVLQ10R Freescale Semiconductor, MK30DN512ZVLQ10R Datasheet - Page 46

• Manufacturer Part Number: MK30DN512ZVLQ10R
• Description: ARM Microcontrollers - MCU KINETIS 512K LCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLQ10R

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Peripheral operating requirements and behaviors
1. Typical values assume V
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
4. Gain = 2
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
6.6.2 CMP and 6-bit DAC electrical specifications
46
Symbol
SINAD
Symbol
V
ENOB
V
function of input common mode voltage (V
PGA reference voltage and gain setting.
I
I
V
V
CMPOh
V
DDHS
CMPOl
t
DDLS
V
DHS
AIN
AIO
DD
H
PGAG
Effective number
of bits
Signal-to-noise
plus distortion
ratio
Description
Supply voltage
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
Analog input offset voltage
Analog comparator hysteresis
Output high
Output low
Propagation delay, high-speed mode (EN=1,
PMODE=1)
Description
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
Table 31. Comparator and 6-bit DAC electrical specifications
Table 30. 16-bit ADC with PGA characteristics (continued)
DDA
K30 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
=3.0V, Temp=25°C, f
See ENOB
Conditions
• Gain=1, Average=4
• Gain=64, Average=4
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
1
Table continues on the next page...
CM
) and the PGA gain.
ADCK
=6MHz unless otherwise stated.
11.6
12.8
11.0
Min.
7.2
7.9
7.3
6.8
6.8
7.5
6.02 × ENOB + 1.76
V
V
SS
DD
1.71
Min.
20
—
—
—
—
—
—
—
—
– 0.3
– 0.5
Typ.
13.4
14.5
14.3
13.8
13.1
12.5
11.5
10.6
9.6
1
Typ.
10
20
30
50
—
—
—
—
—
—
—
5
Max.
—
—
—
—
—
—
—
—
—
Freescale Semiconductor, Inc.
Unit
bits
bits
bits
bits
bits
bits
bits
bits
bits
dB
Max.
V
200
200
3.6
0.5
20
20
—
—
—
—
—
DD
mode,f
differential
Notes
16-bit
in
Unit
mV
mV
mV
mV
mV
=100Hz
μA
μA
ns
V
V
V
V