MK30DN512ZVLQ10R Freescale Semiconductor, MK30DN512ZVLQ10R Datasheet - Page 60

• Manufacturer Part Number: MK30DN512ZVLQ10R
• Description: ARM Microcontrollers - MCU KINETIS 512K LCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLQ10R

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Peripheral operating requirements and behaviors
60
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Num
Num
S10
S11
S12
S13
S14
S15
S16
S17
S18
S1
S2
S3
S4
S5
S6
S7
S8
S9
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
Operating voltage
I2S_BCLK cycle time (input)
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
I2S_RXD hold after I2S_BCLK
Description
Description
Table 46. I
Table 47. I
S15
S15
K30 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
S12
S13
Figure 26. I
S17
2
S master mode timing (full voltage range)
2
S slave mode timing (full voltage range)
S11
S18
2
S timing — slave modes
S12
S16
S15
2 x t
5 x t
8 x t
1.71
45%
45%
23.9
1.71
45%
Min.
Min.
-4.3
-4.6
3.5
10
10
—
—
—
0
0
2
SYS
SYS
SYS
Freescale Semiconductor, Inc.
Max.
55%
55%
Max.
55%
28.6
3.6
3.6
15
15
—
—
—
—
—
—
—
—
—
—
—
S14
MCLK period
MCLK period
BCLK period
S16
S16
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V