MPC8536EBVTATLA Freescale Semiconductor, MPC8536EBVTATLA Datasheet - Page 7

• Manufacturer Part Number: MPC8536EBVTATLA
• Description: Microprocessors - MPU 8536 ENCRYPTED
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536EBVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

Freescale Semiconductor
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MVREF
MDQS
MDQS
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
GND
[26]
[30]
[25]
[29]
[11]
[15]
[12]
[3]
[1]
[9]
[8]
[0]
A
MDQS
MDQS
MDM
MDM
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
GND
LDP
[31]
[24]
[28]
[10]
[14]
[13]
[3]
[3]
[1]
[1]
[5]
[1]
[2]
B
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
AVDD_
MDQS
MDQS
GV DD
GV DD
GV DD
MDM
GND
MDQ
GND
MDQ
GND
LBIU
LAD
[19]
[25]
NC
[2]
[2]
[0]
[0]
C
LSYNC_
LSYNC_
MDQS
GV DD
GV DD
MDQ
GND
MDM
MDQ
MDQ
MDQ
GND
MDQ
GND
OUT
[23]
[17]
[2]
[3]
[6]
[0]
[4]
IN
D
MDQS
GV DD
GV DD
MDQ
MDQ
MDQ
GND
GND
LAD
LAD
LDP
LAD
LAD
LAD
[18]
[16]
[27]
[24]
[22]
[21]
[20]
[2]
[7]
[3]
E
Figure 5. Chip Pin Map Detail C
GV DD
BV DD
BV DD
MDQ
GND
MDQ
MDQ
GND
GND
LAD
LAD
LAD
LAD
LAD
[22]
[21]
[20]
[29]
[23]
[19]
[18]
[17]
F
LGPL2/
LFRE
DETAIL C
GND
GND
GND
LOE/
LCS
LCS
LAD
LAD
LAD
LAD
LAD
LAD
LDP
[31]
[31]
[30]
[28]
[26]
[16]
[15]
[4]
LA
[1]
[1]
G
LWE[3]/
LWE[1]/
LWE[2]/
LGPL3/
LBS[3]
LBS[1]
LBS[2]
DREQ2
LFWP
BV DD
MDIC
LCLK
LCLK
LCS5/
DMA_
LCS
LCS
LAD
LAD
[30]
[14]
[13]
[0]
LA
[2]
[3]
[0]
[2]
H
LGPL0/
LFCLE
LBCTL
LWE0/
LFWE
DACK2
BV DD
BV DD
LBS0/
BV DD
BV DD
LCLK
LALE
LCS6/
DMA_
GND
GND
GND
LAD
[12]
[1]
J
LGPL1/
LGPL5
LFALE
MDIC
GND
LCS
LAD
LAD
LAD
LAD
LDP
LAD
LAD
[28]
[29]
[11]
[10]
LA
LA
[1]
[0]
[0]
[3]
[4]
[7]
[0]
K
LUPWAIT/
DDONE2
LPBSE/
LGPL4/
CORE
BV DD
VDD_
LGTA/
DMA_
LFRB
GND
GND
LCS7/
GND
LAD
LAD
LAD
LAD
LAD
LAD
[27]
Pin Assignments and Reset States
LA
[1]
[2]
[5]
[6]
[9]
[8]
L
IMP_CAL
SD1_TX
SD1_TX
CORE
XGND
XV DD
XGND
SV DD
SGND
VDD_
VDD_
VDD_
SD1_
GND
PLAT
GND
PLAT
_RX
NC
[0]
[0]
M
SD1_RX
SD1_RX
SD1_TX
SD1_TX
CORE
XGND
SGND
VDD_
VDD_
XV DD
SV DD
PLAT
GND
GND
GND
NC
[1]
[1]
[0]
[0]
N
SD1_TX
SD1_TX
SD1_RX
SD1_RX
CORE
XGND
SGND
SGND
VDD_
VDD_
VDD_
XV DD
SV DD
PLAT
PLAT
GND
GND
[2]
[2]
[1]
[1]
P
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