74AUP1T45GF,132 NXP Semiconductors, 74AUP1T45GF,132 Datasheet
74AUP1T45GF,132
Specifications of 74AUP1T45GF,132
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74AUP1T45GF,132 Summary of contents
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Low-power dual supply translating transceiver; 3-state Rev. 5 — 9 August 2012 1. General description The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a direction control input (DIR) and dual supply pins (V ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74AUP1T45GW 40 C to +125 C 74AUP1T45GM 40 C to +125 C 74AUP1T45GF 40 C to +125 C 74AUP1T45GN 40 C to +125 C 74AUP1T45GS 4. Marking Table 2. Marking ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AUP1T45 CC(A) CC(B) GND 2 5 DIR 001aae964 Fig 3. Pin configuration SOT363 6.2 Pin description Table 3. Pin description Symbol Pin V 1 CC(A) GND DIR CC(B) 7. Functional description [1] Table 4. Function table Supply voltage Input DIR ...
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... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage A CC(A) V supply voltage B CC(B) I input clamping current IK V input voltage I I output clamping current OK V output voltage ...
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... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions = 25 C T amb V HIGH-level input data input IH voltage DIR input LOW-level input data input IL voltage DIR input HIGH-level ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I OFF-state output port current V CC(A) I power-off A port; V OFF leakage current V CC(A) B port CC(B) DIR input CC(A) I additional A port; V OFF power-off V CC(A) leakage current B port ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions = 40 C to +85 C T amb V HIGH-level input data input IH voltage DIR input LOW-level input data input IL voltage DIR input ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I power-off A port; V OFF leakage current V CC(A) B port CC(B) DIR input CC(A) I additional A port; V OFF power-off V CC(A) leakage current B port CC(B) DIR input CC(A) I supply current A port ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level input data input IL voltage DIR input HIGH-level output voltage LOW-level ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I additional A port; V OFF power-off V CC(A) leakage current B port CC(B) DIR input CC(A) I supply current A port port plus B port ( GND or V ...
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... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions CC(A) t propagation delay see disable time DIR to A; see dis DIR to B ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t disable time DIR to A; see dis DIR to B; see CC(A) t propagation delay see ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t disable time DIR to A; see dis DIR to B; see CC(A) t propagation delay see ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t disable time DIR to A; see dis DIR to B; see CC(A) t propagation delay see ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t disable time DIR to A; see dis DIR to B; see CC(A) t propagation delay see ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t disable time DIR to A; see dis DIR to B; see CC(A) t propagation delay see ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t disable time DIR to A; see dis DIR to B; see CC(A) t propagation delay see ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t disable time DIR to A; see dis DIR to B; see CC(A) t propagation delay see ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t disable time DIR to A; see dis DIR to B; see CC(A) t propagation delay see ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t disable time DIR to A; see dis DIR to B; see CC(A) t propagation delay see ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t disable time DIR to A; see dis DIR to B; see 74AUP1T45 Product data sheet Low-power dual supply translating transceiver; 3-state … ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions pF and power dissipation A port; (direction capacitance port; (direction port; (direction ...
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... NXP Semiconductors 12. Waveforms Measurement points are given in V and V are typical output voltage drops that occur with the output load Fig 6. The data input ( output (B, A) propagation delay times DIR input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF ...
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... NXP Semiconductors Test data is given in Table R = Load resistance Load capacitance including jig and probe capacitance Termination resistance External voltage for measuring switching times. EXT Fig 8. Test circuit for measuring switching times Table 10. Test data Supply voltage Input [ ...
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... NXP Semiconductors 13. Application information 13.1 Unidirectional logic level-shifting application The circuit given in unidirectional logic level-shifting application. Fig 9. Table 11. Pin 74AUP1T45 Product data sheet Low-power dual supply translating transceiver; 3-state Figure example of the 74AUP1T45 being used CC1 ...
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... NXP Semiconductors 13.2 Bidirectional logic level-shifting application Figure 10 application. Since the device does not have an output enable (OE) pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. V CC1 PULL-UP/DOWN OR I/O-1 BUSHOLD DIR CTRL System-1 System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down. ...
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... NXP Semiconductors 13.3 Power-up considerations A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies. Take the following precautions to guard against such power-up problems: • Connect ground before any supply voltage is applied. • Power-up V • V CC(B) 13.4 Enable times Calculate the enable times for the 74AUP1T45 using the following formulas: • ...
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... NXP Semiconductors 14. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 1.1 0.30 0.25 mm 0.1 0.8 0.20 0.10 OUTLINE VERSION IEC SOT363 Fig 11. Package outline SOT363 (SC-88) 74AUP1T45 Product data sheet Low-power dual supply translating transceiver; 3-state ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. (2) terminal 1 index area Dimensions (mm are the original dimensions) (1) Unit max 0.5 0.04 0.25 1.50 mm nom 0.20 1.45 min 0.17 1.40 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 13. Package outline SOT891 (XSON6) ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1115 Fig 14. Package outline SOT1115 (XSON6) ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1202 Fig 15. Package outline SOT1202 (XSON6) ...
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... NXP Semiconductors 15. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 16. Revision history Table 14. Revision history Document ID Release date 74AUP1T45 v.5 20120809 • Modifications: Package outline drawing of SOT886 74AUP1T45 v.4 20111128 • ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... Low-power dual supply translating transceiver; 3-state NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 11 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 13 Application information ...