CAT64LC40WI-GT3 ON Semiconductor, CAT64LC40WI-GT3 Datasheet
CAT64LC40WI-GT3
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CAT64LC40WI-GT3 Summary of contents
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... LOGIC CS CLOCK SK GENERATOR Figure 1. Block Diagram *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 September, 2009 − Rev. 4 Pin Name ADDRESS DECODER OUTPUT ...
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RDY/BUSY RESET GND PDIP−8 (P, L) Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground (Note ...
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Table 4. D.C. OPERATING CHARACTERISTICS Symbol Parameter I Operating Current CC EWEN, EWDS, READ I Program Current CCP I (Note 6) Standby Current SB I Input Leakage Current LI I Output Leakage Current LO V Low Level Input Voltage, DI ...
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Table 6. POWER−UP TIMING (Notes 8 and 9) Symbol t Power−Up to Read Operation PUR t Power−Up to Program Operation PUW 8. This parameter is tested initially and after a design or process change that affects the parameter ...
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Device Operation The CAT64LC40 nonvolatile memory intended for use with all standard controllers. The CAT64LC40 is organized in a 256 x 16 format. All instructions are based on an 8−bit format. There are four 16−bit instructions: ...
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The CAT64LC40 requires an active LOW CS in order to be selected. Each instruction must be preceded by a HIGH−to−LOW transition of CS before the input of the 4−bit start sequence. Prior to the 4−bit start sequence (1010), the device ...
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An alternative to get RDY/BSY status is from the DO pin. During a write cycle, asserting a LOW input to the CS pin will cause the DO pin to output the RDY/BSY status. Bringing CS HIGH will bring the DO ...
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Reset The RESET pin, when set to HIGH, will reset or abort a WRITE operation. When RESET is set to HIGH while the WRITE instruction is being entered, the device will not execute the WRITE instruction and will keep DO ...
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PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...
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PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...
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E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...
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... Orderable Part Number (for Pb−Free Devices) CAT64LC40LI−GT3 CAT64LC40VI−GT3 CAT64LC40WI−GT3 CAT64LC40YI−GT3 14. All packages are RoHS−compliant (Lead−free, Halogen−free). 15. The standard lead finish is NiPdAu. 16. The device used in the above example is a 64LC40VI−GT3 (SOIC, Industrial Temperature, Tape & Reel). ...