CAT64LC40WI-GT3 ON Semiconductor, CAT64LC40WI-GT3 Datasheet - Page 6

• Manufacturer Part Number: CAT64LC40WI-GT3
• Description: EEPROM
• Manufacturer: ON Semiconductor

be selected. Each instruction must be preceded by a
HIGH−to−LOW transition of CS before the input of the
4−bit start sequence. Prior to the 4−bit start sequence (1010),
the device will ignore inputs of all other logical sequence.
Read
into the DI pin), the DO pin will output data one t
falling edge of the 16th clock (the last bit of the address
field). The READ operation is not affected by the RESET
input.
RDY/BUSY
*Please check instruction set table for address.
RDY/BUSY
The CAT64LC40 requires an active LOW CS in order to
Upon receiving a READ command and address (clocked
RESET
RESET
DO
CS
DO
SK
SK
CS
DI
DI
WRITE INSTRUCTION
1
0
HIGH
LOW
1
0
0
Figure 6. Ready/BUSY Status Instruction Timing
1
Figure 5. Write Instruction Timing
0
PD
0
after the
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ADDRESS*
6
Write
device goes into the AUTO−Clear cycle and then the
WRITE cycle. The RDY/BSY pin will output the BUSY
status (LOW) one t
(the last data bit) and will stay LOW until the write cycle is
complete. Then it will output a logical “1” until the next
WRITE cycle. The RDY/BSY output is not affected by the
input of CS.
After receiving a WRITE op code, address and data, the
D15
SV
D0
NEXT INSTRUCTION
after the rising edge of the 32
nd
clock