CAT64LC40WI-GT3 ON Semiconductor, CAT64LC40WI-GT3 Datasheet - Page 4

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CAT64LC40WI-GT3

Manufacturer Part Number
CAT64LC40WI-GT3
Description
EEPROM
Manufacturer
ON Semiconductor
Datasheet

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8. This parameter is tested initially and after a design or process change that affects the parameter.
9. t
10. (Write All Locations) is a test mode operation and is therefore not included in the AC/DC Operations specifications.
11. Input Rise and Fall Times (10% to 90%) < 10 ns.
12. Input Pulse Levels = V
13. Input and Output Timing Reference = V
Table 6. POWER−UP TIMING
Table 7. WRITE CYCLE LIMITS
Table 8. INSTRUCTION SET
Read
Write
Write Enable
Write Disable
[Write All Locations] (Note 10)
PUR
V
V
Symbol
Symbol
CC
CC
t
t
t
PUW
PUR
WR
and t
x 0.8
x 0.2
Instruction
PUW
are the delays required from the time V
Power−Up to Read Operation
Power−Up to Program Operation
Program Cycle Time
Figure 2. AC Testing Input/Output Waveform
INPUT PULSE LEVELS
CC
x 0.2 and V
(Notes 8 and 9)
CC
CC
x 0.8.
x 0.3 and V
10101000
10100100
10100011
10100000
10100001
Opcode
Parameter
Parameter
CC
CC
http://onsemi.com
x 0.7.
is stable until the specified operation can be initiated.
4
V
V
CC
CC
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
x 0.7
x 0.3
(Notes 11, 12 and 13) (C
X X X X X X X X
X X X X X X X X
X X X X X X X X
Address
4.5 V − 6.0 V
2.5 V
REFERENCE POINTS
L
Min
Min
= 100 pF)
D15 − D0
D15 − D0
D15 − D0
Max
Max
Data
10
10
1
5
Units
Units
ms
ms
ms

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