M24C64-DFMN6TP STMicroelectronics, M24C64-DFMN6TP Datasheet - Page 29
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M24C64-DFMN6TP
Manufacturer Part Number
M24C64-DFMN6TP
Description
EEPROM 64 Kbit Serial I2C 1.7V to 5.5V EEPROM
Manufacturer
STMicroelectronics
Datasheet
1.M24C64-WBN6.pdf
(42 pages)
Specifications of M24C64-DFMN6TP
Product Category
EEPROM
Rohs
yes
Available stocks
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Part Number
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M24C64-W M24C64-R M24C64-F M24C64-DF
Table 16.
1. Characterized only, not tested in production.
2. With C
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
5. The previous product identified by process letter P was specified with t
6. t
7. WC=0 set up time condition to enable the execution of a WRITE command.
8. WC=0 hold time condition to enable the execution of a WRITE command.
9. The previous M24C64 device (identified by process letter P) offers t
t
t
t
DHWH
WLDL
QL1QL2
Symbol
t
t
t
t
XH1XH2
CLQX
CLQV
XL1XL2
t
t
t
t
t
t
t
t
t
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
rising edge of SDA.
offer a safe margin compared to the I
0.7V
M24C64 device offers t
minimum value recommended by the I
CHDH
CHCL
CLCH
DXCH
CHDL
DHDL
CLDX
NS
C
CLQV
DLCL
t
f
W
C
< 400 kHz.
(7)(1)
(1)
(8)(1)
CC
(4)
(6)
(1)
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3V
L
, assuming that R
= 10 pF.
t
t
t
t
t
400 kHz AC characteristics
t
t
SU:STO
SU:DAT
HD:DAT
SU:STA
HD:STA
SU:WC
HD:WC
t
t
f
t
HIGH
Alt.
t
LOW
t
t
BUF
SCL
WR
t
DH
t
t
AA
R
F
F
Clock frequency
Clock pulse width high
Clock pulse width low
SDA (out) fall time
Input signal rise time
Input signal fall time
Data in set up time
Data in hold time
Data out hold time
Clock low to next data valid (access time)
Start condition setup time
Start condition hold time
Stop condition set up time
Time between Stop condition and next Start
condition
WC set up time (before the Start condition)
WC hold time (after the Stop condition)
Internal Write cycle duration
Pulse width ignored (input filter on SCL and
SDA) - single glitch
NS
bus
= 80 ns (max). Both products offer a safe margin compared to the 50 ns
× C
bus
Doc ID 16891 Rev 27
time constant is within the values specified in
2
C specification recommendations.
2
C specification.
Parameter
NS
CLQX
= 100 ns (max), while the current
= 200 ns (min). Both values
100
1300
1300
20
Min.
DC and AC parameters
600
100
600
600
600
(3)
(3)
0
0
1
-
-
-
-
Figure
(2)
(5)
13.
Max.
80
400
300
900
(3)
(3)
5
-
-
-
-
-
-
-
-
-
-
-
(9)
CC
or
Unit
kHz
29/42
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns