M24C32-FMB5TG STMicroelectronics, M24C32-FMB5TG Datasheet - Page 13
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M24C32-FMB5TG
Manufacturer Part Number
M24C32-FMB5TG
Description
EEPROM 32Kbit 100kHz I2C 400 kHZ Fast-Mode
Manufacturer
STMicroelectronics
Datasheet
1.M24C32-FDW6TP.pdf
(40 pages)
Specifications of M24C32-FMB5TG
Product Category
EEPROM
Rohs
yes
Memory Size
32 Kbit
Organization
4 K x 8
Data Retention
40 yr
Maximum Clock Frequency
0.4 MHz
Maximum Operating Current
3 mA
Operating Supply Voltage
1.8 V , 2.5 V , 3.3 V , 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
UFDFPN
Access Time
900 ns
Interface Type
I2C
Minimum Operating Temperature
- 20 C
Supply Voltage - Max
5.5 V
Supply Voltage - Min
1.7 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M24C32-FMB5TG
Manufacturer:
ST
Quantity:
500
Company:
Part Number:
M24C32-FMB5TG
Manufacturer:
MAXIM
Quantity:
142
Part Number:
M24C32-FMB5TG
Manufacturer:
ST
Quantity:
20 000
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
4.5
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in
Table 2.
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared .
When the device select code is received, the device only responds if the Chip Enable
address is the same as the value on its Chip Enable E2,E1,E0 inputs.
The 8
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
the device select code, the device deselects itself from the bus, and goes into Standby
mode.
Device select code
when addressing the
memory array
Device select code
when accessing the
Identification page
Table 2
th
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
(on Serial Data (SDA), most significant bit first).
Device select code
b7
1
1
Device type identifier
Doc ID 4578 Rev 21
b6
0
0
b5
1
1
(1)
th
b4
0
1
bit time. If the device does not match
Chip Enable address
b3
E2
E2
E1
E1
b2
Device operation
b1
E0
E0
(2)
RW
RW
RW
b0
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