LFE3-35EA-7LFN484C Lattice, LFE3-35EA-7LFN484C Datasheet - Page 70

• Manufacturer Part Number: LFE3-35EA-7LFN484C
• Description: FPGA - Field Programmable Gate Array 33.3K LUTs 295 I/O 1.2V -7 SPEED
• Manufacturer: Lattice

Specifications of LFE3-35EA-7LFN484C

• Rohs: yes
• Number Of Gates: 33 K
• Number Of Logic Blocks: 72
• Embedded Block Ram - Ebr: 1327 Kbit
• Number Of I/os: 295
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-484
• Distributed Ram: 68 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 53.7 mA
• Factory Pack Quantity: 60

LatticeECP3 External Switching Characteristics (Continued)
t
f
t
t
t
t
t
f
t
t
t
t
t
f
t
t
t
t
t
f
General I/O Pin Parameters Using Dedicated Clock Input Primary Clock with PLL with Clock Injection Removal Setting
t
t
t
t
t
t
t
H_DEL
MAX_IO
CO
SU
H
SU_DEL
H_DEL
MAX_IO
CO
SU
H
SU_DEL
H_DEL
MAX_IO
CO
SU
H
SU_DEL
H_DEL
MAX_IO
COPLL
SUPLL
HPLL
SU_DELPLL
H_DELPLL
COPLL
SUPLL
Parameter
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock Frequency of I/O and PFU
Register
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock Frequency of I/O and PFU
Register
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock Frequency of I/O and PFU
Register
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock Frequency of I/O and PFU
Register
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Description
Over Recommended Commercial Operating Conditions
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
Device
3-17
Min. Max. Min. Max. Min. Max. Min. Max.
0.0
0.0
1.4
1.3
0.0
0.0
1.2
1.3
0.0
0.7
0.8
1.6
0.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-9
500
500
500
DC and Switching Characteristics
3.8
3.7
3.3
0.0
3.3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LatticeECP3 Family Data Sheet
0.0
0.0
1.4
1.3
0.0
0.0
1.2
1.3
0.0
0.0
1.3
1.3
0.0
0.7
0.8
1.6
0.7
—
—
—
—
—
—
—
—
—
—
-8
500
500
500
500
3.8
3.7
3.5
3.3
0.0
3.3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.0
0.0
1.6
1.5
0.0
0.0
1.4
1.4
0.0
0.0
1.5
1.4
0.0
0.8
0.9
1.8
0.8
—
—
—
—
—
—
—
—
—
—
1, 2
-7
420
420
420
420
4.2
4.1
3.9
3.6
0.0
3.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.0
0.0
1.8
1.7
0.0
0.0
1.6
1.5
0.0
0.0
1.6
1.5
0.0
0.9
1.0
2.0
0.9
—
—
—
—
—
—
—
—
—
—
2
-6
375
375
375
375
4.6
4.5
4.3
0.0
3.8
39
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns