PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 119
PCI-MT32-XP-N1
Manufacturer Part Number
PCI-MT32-XP-N1
Description
FPGA - Field Programmable Gate Array PCI Master/Target 32B
Manufacturer
Lattice
Datasheet
1.PCI-MT32-O4-N2.pdf
(193 pages)
Specifications of PCI-MT32-XP-N1
Factory Pack Quantity
1
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Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-46. 32-bit Target Fast Back-to-Back Transaction (Continued)
CLK
10
12
13
9
Wait
Data 1
Termination
Idle
PCI Data
Phase
If the DEVSEL_TIMING is set to slow, the Core asserts devseln on the clock after bar_hit. If
the back-end will be ready to write data in two cycles, it can assert lt_rdyn.
trdyn is asserted since lt_rdyn was asserted the previous cycle.
If both irdyn and trdyn are asserted on the previous cycle, the master relinquishes control of
framen, ad[31:0] and cben[3:0]. It also de-asserts irdyn if both trdyn and irdyn were
asserted last cycle.
The Core relinquishes devseln and trdyn.
119
Description
Functional Description
PCI IP Core User’s Guide
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