PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 13

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Local Target Control
The Local Target Control responds to target transactions on the PCI bus. Fully decoded BAR select signals
(bar_hit) and new capabilities select signal (new_cap_hit) are provided by the Local Target Control to indicate
that the PCI IP core has been selected for a transaction. Registered address and command signals are available at
the Local Interface from the Local Interface Control for the back-end application to properly handle the core’s
request. Additionally, the Local interface also supplies Configuration Space Register signals and a local interrupt
request (l_interruptn) for users’ applications. A full list of Local Interface signals and descriptions is available in
the Local Interface Signals section.
Configuration Space
The Configuration Space implements all the necessary Configuration Space registers required to support a single-
function PCI IP core. It provides the first 64 bytes of header type 0, which is used for all device types other than
PCI-to-PCI and CardBus bridges. The first 64 bytes of the predefined header region contain fields that uniquely
identify the device and allow the device to be generically controlled. This predefined header portion of the Configu-
ration Space is divided into two parts. The first 16 bytes of the header are defined the same way regardless of the
type of device. The remaining bytes have different definitions depending on the functionality that the PCI IP core
supports. These bytes include six Base Address Registers (BARs), the Capabilities Pointer (Cap Ptr), and the reg-
isters that control the interrupt capability. Refer to the Configuration Space Set-up section for additional information
on the Configuration Space.
Accesses to the first 64 bytes of the Configuration Space are completed by the PCI IP core control with no interven-
tion from the Local Target Interface control. Access beyond the first 64 bytes, such as the Capabilities List, is left to
the Local Target Interface control. These transactions are described in the Advanced Configuration Accesses sec-
tion.
Parity Generator and Checker
Parity checking must occur on every PCI address and data cycle to be compliant with the PCI Local Bus Specifica-
tion, Revision 3.0. The PCI IP core’s Parity Generator and Checker module does all parity checking for the PCI
device. The Parity Generator and Checker determines if the master is successful in addressing the desired target.
It also verifies that data transfers occur correctly between the master and target devices. The address and byte
enable signals are included in every calculation to ensure accuracy. Each address and data cycle that occurs on
the PCI bus is checked for errors.
The parity check signals perrn and serrn are enabled or disabled using bit 6 and bit 8 of the PCI Command Reg-
ister, which is part of the Configuration Space.
Signal Descriptions
Pin Assignments for the evaluation configurations are shown
Final selection of the pinouts is left to the designer to allow for maximum flexibility in the design. Pinouts are
defined in the HDL source code, or as follows:.
• In Diamond, choose View > Show Views > File List, double-click the.lpf file, and edit the file to add pin location
• In ispLEVER, double-click Edit Preference (ASCII) in the Processes window, and edit the file in the Text Editor
Refer to the Diamond or ispLEVER software help for additional information.
There are five types of signals defined in
preferences.
to add pin location preferences.
Table
2-2.
13
“Pin Assignments For Lattice FPGAs” on page
Functional Description
PCI IP Core User’s Guide
161.