1894K-32LF IDT, 1894K-32LF Datasheet - Page 5

• Manufacturer Part Number: 1894K-32LF
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894K-32LF

• Rohs: yes
• Part # Aliases: ICS1894K-32LF

Strapping Options
Functional Description
The ICS1894-32 is an ethernet PHYceiver. During data
transmission, it accepts sequential nibbles/di-bits from the
MAC (Media Access Control), converts them into a serial bit
stream, encodes them, and transmits them over the medium
through an external isolation transformer. When receiving
data, the ICS1894-32 converts and decodes a serial bit
stream (acquired from an isolation transformer that
interfaces with the medium) into sequential nibbles/di-bits. It
subsequently presents these nibbles/di-bits to the MAC
Interface.
The ICS1894-32 implements the OSI model’s physical
layer, consisting of the following, as defined by the ISO/IEC
8802-3 standard:
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Number
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Pin
14
15
11
31
32
16
17
18
20
21
22
1. IO/Ipu = Digital Input with internal 20k pull-up during power on reset/hardware reset; output pin otherwise.
2. IO/Ipd = Digital Input with internal 20k pull-down during power on reset/hardware reset; output pin otherwise.
3. If RXTRI/RXD1 pin is latched high during power on reset/hardware reset, P1/ISO/LED1 functions as RX real time
ANSEL/RXCLK
SPEED/TXCLK
isolation control input after latch and LED1 function will be disabled.
AMDIX/RXD3
P1/ISO/LED1
RXTRI/RXD1
FDPX/RXD0
NOD/RXER
RMII/RXDV
P3/RXD2
P0/LED0
P2/INT
Name
Pin
Type
IO/Ipu
IO/Ipd
IO/Ipd
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipu
Pin
IO
IO
1
1 = AMDIX enable
0 = AMDIX disable
The PHY address is set by P[3:0] at power-on reset. P0 and P1 must have external
pull-up or pull-down to set address at start up.
1 = Real time receiver isolation function enable
1=Full duplex
0=Half duplex (mode not supported)
Ignored if Auto negotiation is enabled
1 = RMII mode
0 = MII mode
1=Enable auto negotiation
0=Disable auto negotiation
0=Node mode
1=repeater mode (mode not supported)
1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
The ICS1894-32 is transparent to the next layer of the OSI
model, the link layer. The link layer has two sublayers: the
Logical Link Control sublayer and the MAC sublayer. The
ICS1894-32 can interface directly with the MAC via MII/RMII
interface signals.
The ICS1894-32 transmits framed packets acquired from its
MAC Interface and receives encapsulated packets from
another PHY, which it translates and presents to its MAC
Interface.
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•
•
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Pin Function
5
Physical Coding sublayer (PCS)
Physical Medium Attachment sublayer (PMA)
Physical Medium Dependent sublayer (PMD)
Auto-Negotiation sublayer
3
; 0 = Receiver Tristate Disable
ICS1894-32
PHYCEIVER
REV M 021512