KSZ8851-16MLLU TR Micrel, KSZ8851-16MLLU TR Datasheet - Page 28
KSZ8851-16MLLU TR
Manufacturer Part Number
KSZ8851-16MLLU TR
Description
Ethernet ICs Single-Port Ethernet Controller (Automotive Grade)
Manufacturer
Micrel
Datasheet
1.KSZ8851-16MLLU.pdf
(83 pages)
Specifications of KSZ8851-16MLLU TR
Rohs
yes
Product
Ethernet Controllers
Package / Case
LQFP-48
Mounting Style
SMD/SMT
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(0x72) register.
Since multiple packets can be pipelined into the TX packet memory for transmit, the transmit status reflects the status of
the packet that is currently being transferred on the MAC interface, which may or may not be the last queued packet in the
TX queue.
The transmit control word is the first 16-bit word in the TX packet memory, followed by a 16-bit byte count. It must be word
aligned. Each control word corresponds to one TX packet. Table 6 gives the transmit control word bit fields.
The transmit Byte Count specifies the total number of bytes to be transmitted from the TXQ. Its format is given in Table 7.
The data area contains six bytes of Destination Address (DA) followed by six bytes of Source Address (SA), followed by a
variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
KSZ8851-16MLL does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by
the KSZ8851-16MLL. It is treated transparently as data both for transmit operations.
May 2012
Micrel, Inc.
Bit
15-11
10-0
Bit
15
14-6
5-0
Packet Memory Address Offset
Description
TXIC Transmit Interrupt on Completion
When this bit is set, the KSZ8851-16MLL sets the transmit interrupt after the present frame has been
transmitted.
Reserved.
TXFID Transmit Frame ID
This field specifies the frame ID that is used to identify the frame and its associated status information
in the transmit status register.
Description
Reserved.
TXBC Transmit Byte Count
Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer memory
for better utilization of the packet memory.
Note: The hardware behavior is unknown if an incorrect byte count information is written to this field.
Writing a 0 value to this field is not permitted.
4 - up
0
2
Table 5. Frame Format for Transmit Queue
Table 6. Transmit Control Word Bit Fields
Table 7. Transmit Byte Count Format
Bit 15
2
Control Word
(High byte and low byte need to swap in Big-Endian mode)
Byte Count
(High byte and low byte need to swap in Big-Endian mode)
Transmit Packet Data
(maximum size is 2000)
nd
Byte
28
1
st
Byte
Bit 0
KSZ8851-16MLL/MLLI
M9999-050112-2.1
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