KSZ8851-16MLLU TR Micrel, KSZ8851-16MLLU TR Datasheet - Page 56

• Manufacturer Part Number: KSZ8851-16MLLU TR
• Description: Ethernet ICs Single-Port Ethernet Controller (Automotive Grade)
• Manufacturer: Micrel

Specifications of KSZ8851-16MLLU TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR
The value of this register determines the address to be accessed within the TXQ frame buffer. When the AUTO increment
is set, It will automatically increment the pointer value on write accesses to the data register.
The counter is incremented by one for every byte access, by two for every word access, and by four for every double
word access.
RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR
The value of this register determines the address to be accessed within the RXQ frame buffer. When the Auto Increment
is set, it will automatically increment the RXQ Pointer on read accesses to the data register.
The counter is incremented is by one for every byte access, by two for every word access, and by four for every double
word access.
May 2012
Micrel, Inc.
Bit
4
3
2-1
0
Bit
15
14
13-11
10-0
Bit
15
14
13
Default Value
Default Value
Default Value
0x000
0x0
0x0
0x0
0x0
0x0
-
-
-
-
-
R/W
WO
RW
RW
RW
R/W
R/W
RW
RW
RO
RO
RO
RO
RO
Description
ADRFE Auto-Dequeue RXQ Frame Enable
When this bit is written as 1, the KSZ8851-16MLL will automatically enable RXQ frame buffer
dequeue. The read pointer in RXQ frame buffer will be automatically adjusted to next received
frame location after current frame is completely read by the host.
SDA Start DMA Access
When this bit is written as 1, the KSZ8851-16MLL allows a DMA operation from the host CPU
to access either read RXQ frame buffer or write TXQ frame buffer with CSN and RDN or WRN
signals while the CMD pin is low. All registers access are disabled except this register during
this DMA operation.
This bit must be set to 0 when DMA operation is finished in order to access the rest of registers.
In order to get out of DMA mode the SD1 bit must set to “1” when CMD = 1.
Reserved.
RRXEF Release RX Error Frame
When this bit is written as 1, the current RX error frame buffer is released.
Note: This bit is self-clearing after the frame memory is released. The software should wait for
the bit to be cleared before processing new RX frame.
Description
Reserved.
TXFPAI TX Frame Data Pointer Auto Increment
When this bit is set, the TX Frame data pointer register increments automatically on
accesses to the data register. The increment is by one for every byte access, by two for
every word access, and by four for every doubleword access.
When this bit is reset, the TX frame data pointer is manually controlled by user to access
the TX frame location.
Reserved.
TXFP TX Frame Pointer
TX Frame Pointer index to the Frame Data register for access.
This field reset to next available TX frame location when the TX Frame Data has been
enqueued through the TXQ command register.
Description
Reserved.
RXFPAI RX Frame Pointer Auto Increment
When this bit is set, the RXQ Address register increments automatically on accesses to
the data register. The increment is by one for every byte access, by two for every word
access, and by four for every double word access.
When this bit is reset, the RX frame data pointer is manually controlled by user to access
the RX frame location.
Reserved.
56
KSZ8851-16MLL/MLLI
M9999-050112-2.1