AT25DL081-MHN-T Adesto Technologies, AT25DL081-MHN-T Datasheet - Page 40

• Manufacturer Part Number: AT25DL081-MHN-T
• Description: Flash 8M 1.65-1.95V 100Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT25DL081-MHN-T

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 8 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 1.95 V
• Supply Voltage - Min: 1.65 V
• Maximum Operating Current: 20 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UDFN-8

11.3
Write Status Register Byte 2
The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Status Register. Using the
Write Status Register Byte 2 command is the only way to modify the RSTE and SLE bits in the Status Register during
normal device operation, and the SLE bit can only be modified if the sector lockdown state has not been frozen. Before
the Write Status Register Byte 2 command can be issued, the Write Enable command must have been previously issued
to set the WEL bit in the Status Register to a Logical 1.
To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and then the opcode 31h must be
clocked into the device followed by one byte of data. The one byte of data consists of three don’t-care bits, the RSTE bit
value, the SLE bit value, and three additional don’t-care bits (see
device will be ignored. When the CS pin is deasserted, the RSTE and SLE bits in the Status Register will be modified,
and the WEL bit in the Status Register will be reset back to a Logical 0. The SLE bit will only be modified if the Freeze
Sector Lockdown State command has not been previously issued.
The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be
deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of
the RSTE and SLE bits will not change, and the WEL bit in the Status Register will be reset back to the Logical 0 state.
Table 11-4. Write Status Register Byte 2 Format
Figure 11-3. Write Status Register Byte 2
SCK
CS
SO
Bit 7
SI
X
MSB
High-impedance
0
Bit 6
0
X
0
1
1
2
Opcode
1
3
0
4
0
5
Bit 5
0
6
X
1
7
MSB
X
8
X
9
Status Register In
X
10 11
Byte 2
D
RSTE
Bit 4
D
12
X
13
X
14 15
X
Bit 3
SLE
Table
11-4). Any additional data bytes sent to the
Bit 2
X
AT25DL081 [DATASHEET]
Bit 1
8732E–DFLASH–1/2013
X
Bit 0
X
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